Multi-Pattern IC Metallization for Lower Via Resistance and Capacitance
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Solution Overview
Problem
Narrow metal interconnects in integrated circuits cause high connection resistance and increased circuit capacitance, leading to power consumption and performance issues as transistors become smaller.
Innovation Solution
Implementing multi-pattern metallization to extend one of the source or drain metal lines farther in a direction than the other, providing additional via landing areas to reduce resistance and capacitance without increasing side-to-side capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal interconnects are made narrower to accommodate smaller transistors, then transistor density is improved, but connection resistance increases and power consumption increases
Solution Approach 1:
The patent extends metal interconnects in the first direction (length dimension) beyond what is traditionally done, creating extended portions that provide additional via landing areas. This dimensional extension allows for larger via areas without increasing the side-to-side spacing between interconnects, thereby reducing connection resistance while maintaining high transistor density.
2Productivity
If metal interconnects are made narrower, then transistor density is improved, but circuit capacitance increases and performance slows
Solution Approach 1:
By extending the metal interconnects in the first direction and positioning via landing areas at the extended portions, the patent reduces via-to-via capacitance through increased spacing in the longitudinal direction, while maintaining compact side-to-side spacing to preserve transistor density.
Data Source
AI summary
An integrated circuit (IC) includes transistors formed in diffusion regions. In each transistor, a source and a drain extend in a first direction, and a gate is disposed on the diffusion region between the source and the drain. To reduce connection resistance through at least one of a source metal line and a drain metal line connected to the source and the drain of a transistor, one of the source metal line and the drain metal line extends farther than the other in the first direction to provide additional via landing area to support an interconnection via having reduced resistance without increasing side-to-side capacitance between the source and drain metal lines. Increasing the via landing area reduces connection resistance to the source and/or drain. Providing an extended source metal line and/or drain metal line allows a via landing area to be shifted in the first direction to reduce via capacitance.