Integrated Circuit Micro-Module Using Photo-Imageable Epoxy
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Solution Overview
Problem
Conventional integrated circuit packaging techniques face challenges in creating cost-effective multi-chip modules that efficiently integrate multiple interconnect layers and components, such as integrated circuits, heat sinks, and sensors, while ensuring reliable heat dissipation and precise component placement.
Innovation Solution
The development of integrated circuit micro-modules using multiple layers of photo-imageable epoxy, such as SU-8, with conductive interconnect layers formed through electroplating, and the use of wafer level processing techniques to create a high-performance, cost-effective package that integrates multiple components and provides effective heat dissipation through thermal pipes and heat sinks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional packaging techniques are used to create multi-chip modules, then multiple electronic devices can be integrated into a single package, but the manufacturing cost increases and manufacturing precision decreases
Solution Approach 1:
The patent segments the manufacturing process into distinct sequential steps: depositing epoxy layers, forming openings, placing integrated circuits, and forming conductive interconnect layers. This segmentation allows each step to be optimized independently, improving manufacturing precision while maintaining the capability to integrate multiple electronic devices into a single package.
Solution Approach 2:
The patent applies preliminary action by pre-forming the epoxy layers and openings before placing the integrated circuits. This preliminary preparation ensures precise positioning and alignment of multiple electronic devices, reducing manufacturing complexity and cost while maintaining high integration capability.
2Reliability
If multiple interconnect layers are integrated using laminated films or stacked chip carriers, then connectivity between components is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the formation of multiple conductive interconnect layers into a unified process using sequential epoxy deposition and photolithographic patterning. This combining approach maintains reliable connectivity between components while reducing device complexity by eliminating the need for separate laminated films or stacked chip carriers.
Solution Approach 2:
The patent changes the material parameter from conventional laminated films or chip carriers to photo-imageable epoxy layers. This parameter change enables simpler manufacturing while achieving the same connectivity function, reducing device complexity without compromising reliability.
3Reliability
If conventional packaging methods are used, then basic component protection is provided, but heat dissipation efficiency and component placement precision are insufficient
Solution Approach 1:
The patent introduces photo-imageable epoxy layers as an intermediary material that provides both protective encapsulation and thermal management functionality. This intermediary material protects integrated circuits while enabling improved heat dissipation, addressing both protection and temperature control requirements simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, high-performance packages with efficient heat dissipation and precise component integration, addressing the limitations of existing packaging techniques by providing a cost-effective solution for various applications.
Implementation Method 1
The deposited photoresist layer is photolithographically patterned
Implementation Method 2
A conductive material is electroplated onto the exposed portions of the seed layer
Implementation Method 3
The epoxy layers are deposited using spin coating
Data Source
AI summary
Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed. The integrated circuit is electrically connected with the external package contacts at least in part through one or more of the conductive interconnect layers.