Integrated Circuit Micro-Module with Thermal Pipes
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Solution Overview
Problem
Conventional integrated circuit packaging techniques face challenges in providing cost-effective solutions for diverse packaging applications, particularly in integrating multiple interconnect layers and efficient heat dissipation within a single package.
Innovation Solution
The development of integrated circuit packages composed of stacked layers of planarized, photo-imageable dielectric with interconnect layers and thermal pipes, allowing for the integration of multiple integrated circuits, passive devices, and efficient heat dissipation through conductive vias and thermal pipes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple interconnect layers are integrated into the package using laminated films or stacked chip carriers, then electrical connectivity is improved, but device complexity increases
Solution Approach 1:
The package structure is segmented into multiple planarized dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) with interconnect layers positioned between them. This segmentation allows independent formation and routing of electrical connections at different levels, improving connectivity while maintaining manageable complexity through modular layering.
Solution Approach 2:
The patent transitions from two-dimensional planar packaging to three-dimensional stacked packaging by positioning interconnect layers and integrated circuits at different vertical levels. The first, second, and third dielectric layers are stacked sequentially with interconnect layers in between, creating multiple electrical pathways in the vertical dimension and enhancing connectivity without expanding the package footprint.
2Adaptability or versatility
If multiple integrated circuits are integrated into a single package, then functionality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The integrated circuits are embedded into the dielectric layers during the fabrication process before final package assembly. The first integrated circuit is embedded in the first dielectric layer, and the second integrated circuit is embedded in the second dielectric layer during layer formation. This preliminary embedding ensures precise positioning and reduces alignment requirements in subsequent manufacturing steps.
Solution Approach 2:
Multiple integrated circuits are merged into a single package structure with shared dielectric and interconnect layers. The first integrated circuit and second integrated circuit coexist within the same package, connected through the interconnect layers formed between dielectric layers, achieving functional integration while streamlining the overall package structure.
3Temperature
If thermal pipes are added to conduct heat from the interior to the edges, then heat dissipation is improved, but device complexity increases
Solution Approach 1:
Thermal pipes are introduced as intermediary heat transfer components positioned within the package structure. These thermal pipes conduct heat away from the integrated circuits through the dielectric layers to the package edges where heat can be dissipated. The thermal pipes serve as dedicated thermal pathways that improve heat dissipation efficiency while being integrated into the existing layered structure.
4Manufacturing precision
If planarized photo-imageable dielectric layers are used instead of conventional packaging materials, then manufacturing precision is improved, but ease of manufacture decreases
Solution Approach 1:
Conventional packaging materials are replaced with planarized photo-imageable dielectric layers that can be precisely patterned using photolithography. The photo-imageable property allows for precise definition of interconnect patterns and layer boundaries through light exposure and development processes, significantly improving alignment precision and manufacturing control compared to traditional materials.
Solution Approach 2:
Traditional mechanical assembly and alignment methods are replaced with photo-lithographic patterning processes. The planarized photo-imageable dielectric layers are formed through sequential deposition, photolithographic exposure, and development steps, replacing manual or mechanical alignment operations with automated optical processes that achieve higher precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables cost-effective, high-performance packaging with improved heat dissipation and electrical connectivity, facilitating the integration of various components within a single package while maintaining reliability and precision.
Implementation Method 1
The package can include thermal pipes for conducting heat from the interior to the edges of the package
Implementation Method 2
The integrated circuit may be positioned on the heat sink such that a bottom surface of the integrated circuit is in direct contact with the heat sink
Implementation Method 3
heat sink or heat sinking or heat spreading layers may be formed within the package
Implementation Method 4
conductive vias that extend through corresponding dielectric layers
Implementation Method 5
conductive vias that electrically connect different components of the package
Implementation Method 6
layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating
Implementation Method 7
The epoxy layers are deposited using spin coating. At least some of the layers are photolithographic ally patterned after they are deposited
Data Source
Figure 1
Figure 2
Figure 3A~3E
AI summary
In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, one or more dielectric layers, sensors, optical elements, passive devices and/or a substrate with embedded components. Various methods for forming the aforementioned packages are also described.