IC Vulnerability Assessment via Milling Exclusion Areas
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Solution Overview
Problem
Current security measures for Integrated Circuits (ICs) against microprobing attacks, such as active shields, are costly and ineffective, especially for ICs with fewer routing layers, as they require extensive coverage and are vulnerable to Focused Ion Beam (FIB) tools that can bypass or disable these shields, making it difficult to protect sensitive information.
Innovation Solution
A method to assess the vulnerability of ICs to microprobing attacks by identifying milling exclusion areas based on covering wires and superimposing these areas onto logic nets, allowing for a quantitative evaluation of exposed areas, thereby optimizing protection design without the need for full-layer coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If active shields are designed to cover the entirety of the die, then security protection against microprobing attacks is improved, but design cost and complexity increase prohibitively
Solution Approach 1:
The patent divides the die into multiple rectangular segments representing logic nets, and selectively applies shielding only to vulnerable segments rather than covering the entire die. This segmentation allows targeted protection of critical areas while reducing overall shield complexity and cost.
Solution Approach 2:
The patent implements local quality by making different parts of the die have different protection levels. Critical logic nets receive shielding protection through milling exclusion areas, while non-critical areas remain unprotected. This localized approach optimizes security resources where they are most needed.
2Reliability
If multiple metal routing layers are required for active shields, then security protection is improved, but design cost and manufacturing complexity increase prohibitively
Solution Approach 1:
The patent applies partial action by implementing shielding only for vulnerable logic nets rather than requiring comprehensive multi-layer coverage across the entire IC. The milling exclusion areas provide sufficient protection for critical paths without mandating excessive routing layers throughout the design.
Solution Approach 2:
The patent changes the protection parameter from multi-layer routing to single-layer milling exclusion areas. By defining protected zones through coordinate-based exclusion areas rather than requiring multiple metal layers, the solution reduces manufacturing complexity while maintaining security effectiveness.
3Ease of manufacture
If ICs are fabricated with fewer routing layers, then manufacturing cost is reduced, but vulnerability to microprobing attacks increases
Solution Approach 1:
The patent introduces milling exclusion areas as an intermediary protection mechanism that does not require additional routing layers. These exclusion areas act as a mediator between the limited routing layer structure and the security requirement, providing protection through FIB milling constraints rather than through additional metal layers.
Solution Approach 2:
The patent shifts protection from the routing layer dimension to the spatial coordinate dimension. Instead of adding more metal layers (vertical dimension), the solution defines protected areas through coordinate-based milling exclusion zones in the planar dimension, enabling security without increasing layer count.
4Difficulty of detecting and measuring
If active shields are placed in the top metal layer, then detection capability is improved, but effectiveness against microprobing attacks deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-defining milling exclusion areas during the design phase based on logic net vulnerability analysis. Rather than relying on top-layer shield detection, the protection is proactively embedded into the layout through coordinate-based exclusion zones that prevent FIB milling access to critical areas before an attack can occur.
Data Source
AI summary
A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the logic nets; finding a milling exclusion area based on a covering wire; and superimposing the found milling exclusion area onto the rectangular segments of the logic nets. The milling exclusion area is an area that microprobing attack does not succeed without cutting off at least one of the rectangular segments.