Integrated Circuit Modeling with BEOL RC Data
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Solution Overview
Problem
Current EDA tools are inadequate in modeling integrated circuits, particularly in considering back-end of line (BEOL) components and connections, leading to imprecise pre-layout simulations and increased design time due to difficulties in estimating and tracking resistance-capacitance (RC) values and parasitic effects, which often result in undesirable circuit performance.
Innovation Solution
The method involves modifying process design kit (PDK) files using a macro device application programming interface (API) to include BEOL RC values and selectively color representations of circuit components, allowing for more accurate pre-layout simulations by accounting for parasitic effects and enabling designers to visually assess compliance with design specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional EDA tools are used for pre-layout simulation, then the simulation process is simple and fast, but the modeling precision is insufficient due to inadequate consideration of BEOL components and parasitic effects
Solution Approach 1:
The patent applies preliminary action by integrating BEOL RC extraction and parasitic effect analysis into the pre-layout simulation stage. The system proactively identifies and models parasitic effects before the actual layout is finalized, allowing designers to address these issues early in the design process rather than discovering them later during manufacturing or testing.
Solution Approach 2:
The patent introduces an intermediary mechanism that bridges the gap between simplified conventional EDA tools and the need for accurate BEOL modeling. The system uses an intermediary data structure and calculation methodology that translates complex BEOL parasitic effects into formats that can be processed by standard EDA simulation tools, thereby enabling accurate modeling without requiring complete replacement of existing toolchains.
2Manufacturing precision
If accurate BEOL RC values are incorporated into pre-layout simulation, then design precision is improved, but design time increases due to additional calculations and data processing
Solution Approach 1:
The system performs BEOL RC extraction and parasitic effect calculations during the pre-layout stage itself, rather than as a separate post-processing step. This preliminary action allows accurate modeling data to be prepared in advance, reducing the need for iterative recalculations later in the design process.
Solution Approach 2:
The patent changes the parameters being simulated by introducing BEOL-specific RC values and parasitic effect parameters into the pre-layout simulation framework. By modifying the simulation parameters to include these additional factors, the system achieves higher design precision while utilizing existing simulation infrastructure, thereby minimizing the time penalty associated with new calculations.
3Productivity
If parasitic effects are neglected in pre-layout simulation, then the design process is faster and simpler, but circuit performance becomes undesirable due to unaccounted parasitic impacts
Solution Approach 1:
The patent converts the potentially harmful effect of parasitic impacts into a beneficial design feature by systematically identifying and modeling these effects during pre-layout simulation. Rather than allowing parasitic effects to degrade circuit performance undetected, the system uses them as input data to optimize the design, thereby turning a harmful factor into an opportunity for improvement.
Solution Approach 2:
The system implements feedback by using the extracted BEOL RC values and parasitic effect data to adjust and refine the pre-layout simulation results. This feedback loop allows designers to see the impact of parasitic effects on circuit performance and make necessary design modifications before fabrication, ensuring both speed and reliability.
Data Source
AI summary
A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.