IC Module Address Decoding for Flexible Memory Configuration

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Solution Overview

Problem

Conventional methods for providing different memory configurations in integrated circuits either require disabling unneeded memory in lower-end applications or creating separate silicon mask sets, both of which are costly and complex, especially when dealing with semiconductor wafers that need to be cut into IC dies with varying configurations.

Innovation Solution

An addressing and decoding scheme that allows an external bus master device to access memory mapped resources within an array of IC modules using relative addressing, eliminating the need for programming or customization of the IC modules and enabling flexible configuration without constraining the size of the IC module array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If separate silicon mask sets are created for each memory configuration, then optimal cost efficient memory configuration is achieved for each product, but the overall product cost increases due to multiple mask sets

Engineering Contradiction:
Improvememory configuration efficiencyVSAvoidoverall product cost
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent segments the address decoding function into two parts: a common prefix decoder shared by all IC modules and a suffix decoder local to each module. This segmentation allows a single silicon mask set to serve multiple memory configurations, resolving the contradiction between manufacturing efficiency and cost.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The common prefix decoder is designed to be universal and shared across all IC modules in the array, enabling the same hardware to handle addressing for different memory configurations. This multi-functionality eliminates the need for separate mask sets while maintaining configuration efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If individual select lines are routed to each mapped resource, then precise resource addressing is achieved, but significant cost and complexity is added to inter-module cross-wafer electrical connections

Engineering Contradiction:
Improveresource addressing precisionVSAvoidinter-module connection complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent transitions from a one-dimensional addressing scheme (individual select lines to each resource) to a two-dimensional scheme using address prefixes and suffixes. This dimensional change allows precise resource addressing while significantly reducing the number of inter-module connections required.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple address select lines are merged into a common prefix decoder that is shared across all IC modules. This merging reduces the number of individual connections needed while maintaining the ability to precisely address individual resources within modules.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If custom addresses are assigned using custom metal layers or fuses, then unique addressing for each resource is achieved, but cost and complexity are added to the replicated IC modules

Engineering Contradiction:
Improveaddress uniquenessVSAvoidmodule customization complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Each IC module is equipped with a local suffix decoder that automatically handles the decoding of address suffixes specific to that module. This self-service approach provides unique addressing for each resource without requiring external customization through custom metal layers or fuses, thereby reducing module complexity.

Inventive Principle:
Principle #25Self-service

4Adaptability or versatility

If custom addresses are allocated on system start-up, then flexible addressing is achieved, but significant delay is added to the system start-up procedure

Engineering Contradiction:
Improveaddressing flexibilityVSAvoidsystem start-up delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The address decoding logic, including both prefix and suffix decoding, is pre-configured into the hardware architecture of each IC module. This preliminary action eliminates the need for runtime address allocation, providing addressing flexibility without adding system start-up delays.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10108364B2IC module and method of decoding resource access requests
Publication Date: 2018.10.23 NXP USA INC
  • US10108364B2 patent drawing
  • US10108364B2 patent drawing
  • US10108364B2 patent drawing

AI summary

An integrated circuit (IC) module comprising at least one memory mapped resource, at least one port arranged to be coupled to a further IC module, and an address decoding component. Upon receipt of a resource access request by the IC module, the address decoding component is arranged to extract at least one position parameter from an address field of the received resource access request, determine if the at least one position parameter indicates a target resource as residing within the IC module, and if it is determined that the at least one position parameter indicates the target resource as not residing within the IC module, modify the at least one position parameter to represent a change of one position and forward the resource access request with the modified position parameter over the port to the further IC module.