Integrated Circuit Module Timing Budget Estimation
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Solution Overview
Problem
Current static timing analysis (STA) methods can only be performed after the design and layout of a digital circuit, making it difficult to estimate timing budgets for IC modules early in the design cycle, which can lead to delays in micro-architecture changes and scheduling issues.
Innovation Solution
A method for estimating interface timing paths between IC modules using expected gate-delays, wire-distances, wire-type, and other design considerations based on an early floor-plan, allowing for top-level measurement of module timing budgets and early micro-architecture validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If static timing analysis is performed after design and layout, then timing verification accuracy is improved, but design cycle time increases and micro-architecture changes become difficult
Solution Approach 1:
The patent performs timing analysis at the module level before complete design and layout, using preliminary floor-plan information to estimate timing budgets. This allows timing verification to occur earlier in the design cycle, enabling micro-architecture changes while still maintaining reasonable accuracy through statistical methods rather than waiting for post-layout STA.
2Productivity
If module level timing budgets are estimated early using floor-plan, then design schedule flexibility improves, but timing estimation accuracy may be reduced
Solution Approach 1:
The patent replaces rigorous circuit simulation with statistical timing analysis methods that use floor-plan information, gate-delay estimates, and wire-distance calculations. This substitution provides sufficiently accurate timing budgets early in design while being computationally efficient enough to iterate and adjust schedules, achieving both speed and acceptable accuracy.
3Measurement precision
If rigorous circuit simulation is used for timing measurements, then timing accuracy is improved, but computational speed decreases making it impractical for iterative optimization
Solution Approach 1:
The patent uses simplified timing models and statistical methods that are computationally inexpensive compared to rigorous circuit simulation. These approximate models can be executed rapidly during iterative optimization processes at various design phases, providing sufficient accuracy without the computational burden of full simulation.
Data Source
AI summary
A circuit analysis tool is provided, enabled as computer software instructions, for budgeting time delays between integrated circuit (IC) modules. The instructions accept a command enabling an IC floor-plan including a first module and a second module. The first module includes a first circuit element having a signal output interface, and an output port. The second module includes an input port, and a second circuit element having a signal input interface. A command is accepted defining a maximum delay value, and a first delay value is estimated between the first circuit element signal output interface and the first module output port. A second delay value is estimated between the second circuit element signal input interface and the second module input port, and a third delay value is estimated between the first module output port and the second module input port. The first, second, and third delay values are summed, creating a time budget estimate. The time budget estimate is approved if it is less than the maximum delay value.