Integrated Circuit Identity Verification via Multi-Rate Signature Testing
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Solution Overview
Problem
Conventional semiconductor wafer assembly processes often result in mislabeling of integrated circuit devices due to mixing of bins or wafers, leading to incorrectly labeled finished devices, which can be costly to rectify.
Innovation Solution
A simple method using a low-cost tester with direct memory access (DMA) to execute digital pattern tests at various speeds, applying a sequence of test vectors to determine the correct speed of each integrated circuit, allowing for accurate screening and verification of device labeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional assembly processes use wafer map and probe test results to identify good chips, then manufacturing efficiency is improved, but mislabeling of integrated circuit devices occurs due to mixing of bins or wafers
Solution Approach 1:
The patent applies preliminary action by performing signature tests on integrated circuit devices during the assembly process before final packaging and labeling. The test executes digital patterns at multiple rates to verify device identity and speed characteristics, ensuring correct labeling before devices are packaged. This early detection prevents mislabeled devices from proceeding through the manufacturing process.
Solution Approach 2:
The patent implements feedback by using signature test results to provide information about device characteristics and identity. The test measures device response at different clock rates and compares results against expected signatures for different device types. This feedback mechanism enables real-time verification of device labeling accuracy and allows for corrective action before packaging.
2Adaptability or versatility
If multiple bin numbers are used to categorize die attributes, then manufacturing flexibility is improved, but device mislabeling increases due to bin mixing
Solution Approach 1:
The patent applies parameter changes by testing devices at multiple clock rates (different timing parameters) to create unique signatures for different device types. Instead of relying solely on bin numbers assigned during probe testing, the system varies the test clock rate parameter to elicit different response patterns from devices with different speed characteristics. This provides an additional verification dimension beyond bin categorization.
Solution Approach 2:
The patent performs signature verification as a preliminary action before final packaging and labeling. By executing digital patterns at multiple rates and analyzing device responses early in the assembly process, the system verifies device identity and ensures correct labeling before devices are packaged and shipped, preventing mislabeled devices from reaching customers.
3Productivity
If alignment happens only at the start of each wafer in pick and place equipment, then manufacturing speed is improved, but detection of errors after alignment is lost
Solution Approach 1:
The patent implements feedback by continuously monitoring device performance through signature testing after pick and place assembly. Even though alignment occurs only at the start of each wafer, the system subsequently tests each device's response to digital patterns at multiple clock rates, providing ongoing verification that devices are correctly oriented and functioning as expected, thereby detecting errors that might occur after alignment.
Data Source
AI summary
Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example.