Multiplexer-Based Scan Test Coverage for Integrated Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the complexity and integration of semiconductor integrated circuits increase, existing design for testability (DFT) techniques, particularly the scan test method, struggle to achieve comprehensive test coverage for combinational logic circuits connected to primary input and output terminals, leading to untestable regions and increased design overhead.
Innovation Solution
The proposed integrated circuit design includes a multiplexer within a core block that selectively connects primary input or output signals to flip-flops, allowing for increased test coverage without adding new flip-flops, thereby minimizing design overhead and enabling testing of previously untestable regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan test method is used for testing combinational logic circuits, then testing capability is provided, but test coverage is insufficient for regions connected to primary input and output terminals
Solution Approach 1:
The multiplexer is configured to operate in multiple modes: during normal operation it routes primary input signals to combinational logic circuits, and during test operation it routes scan chain output signals to the same combinational logic circuits. This multi-functionality allows the same hardware structure to serve both operational and testing purposes, improving test coverage without adding dedicated test infrastructure.
Solution Approach 2:
The multiplexer acts as an intermediary component that mediates between the scan chain and the combinational logic circuits. By introducing this intermediary element, the patent enables scan test signals to reach previously untestable regions without directly modifying the combinational logic circuits or adding complex test infrastructure.
2Reliability
If additional flip-flops are added to increase test coverage, then test capability is improved, but area of the core block increases
Solution Approach 1:
Existing flip-flops in the scan chain are made multi-functional by using them to provide test signals to combinational logic circuits during test mode, in addition to their normal data storage function. This eliminates the need to add dedicated test flip-flops, thereby improving test coverage without increasing core block area.
Solution Approach 2:
The patent merges the testing function with the existing data path by using the multiplexer to route scan chain outputs to combinational logic circuits. This consolidation allows testing capabilities to be integrated into the existing hardware structure without adding separate testing components that would increase area.
3Reliability
If multiplexer is added to enable selective signal routing, then test coverage is increased, but device complexity increases
Solution Approach 1:
The multiplexer is controlled by a test control signal that automatically switches between normal operation mode and test mode. This self-service mechanism allows the circuit to autonomously configure its signal routing based on the operational mode, reducing the need for external complex control logic and minimizing the increase in device complexity.
Data Source
AI summary
An integrated circuit may include a plurality of combinational logic circuits including a first combinational logic circuit, a plurality of flip-flops including a first flip-flop configured to receive a first scan input signal and a first data signal, and a first core block including a multiplexer. The multiplexer may be configured to select, based on a test control signal, one of a primary input signal received through a primary input terminal and an output signal of the first flip-flop and provide the selected signal to the first combinational logic circuit. The first flip-flop may be further configured to selectively receive, based on a scan control signal, one of the first scan input signal and the first data signal.