Integrated Circuit Negative Power Supply Mesh Design
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Solution Overview
Problem
The increasing integration of memory cells in integrated circuits leads to increased resistance in lines, causing signal delays and unstable supply of negative supply voltage, which affects the performance of memory devices.
Innovation Solution
The integrated circuit design includes a mesh-shaped pattern across multiple wiring layers to provide a stable negative supply voltage to memory cells, reducing resistance by connecting adjacent power supply line landing pads and increasing the cross-sectional area of via forming the path for the negative supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory cells is increased, then the density and capacity of the integrated circuit are improved, but the resistance of lines increases causing signal delays and unstable voltage supply
Solution Approach 1:
The negative power supply pattern is divided into multiple segments across different wiring layers (first negative power supply pattern on second wiring layer, second negative power supply pattern on third wiring layer). Each segment connects to multiple power supply line landing pads, creating a distributed network that reduces the resistance and improves the stability of voltage supply to memory cells while maintaining high integration density.
2Quantity of substance
If the width and interval of lines are decreased to increase integration, then more memory cells can be packed, but parasitic elements and resistance increase
Solution Approach 1:
The power supply network is extended into the vertical dimension by using multiple wiring layers. The first negative power supply pattern on the second wiring layer and the second negative power supply pattern on the third wiring layer create a three-dimensional power distribution network. This multi-layer approach provides additional pathways for current flow, effectively reducing parasitic resistance without requiring wider lines in the planar dimension, thus maintaining high integration density.
3Use of energy by moving object
If power supply voltage is reduced for reduced power consumption, then energy efficiency is improved, but the effect of parasitic elements and resistance becomes more significant
Solution Approach 1:
The patent creates locally optimized power supply paths by connecting multiple power supply line landing pads to the negative power supply pattern. Each local region has its own dedicated connection points and wiring paths, ensuring that voltage supply quality is maintained locally even when overall power consumption is reduced. This local quality approach minimizes the impact of parasitic elements in each specific memory cell region.
Solution Approach 2:
By utilizing multiple wiring layers vertically, the patent creates redundant and parallel current paths that reduce the effective resistance in each local region. The multi-layer structure allows current to flow through multiple pathways simultaneously, compensating for the reduced voltage headroom and maintaining stable voltage supply despite lower power consumption levels.
Data Source
AI summary
An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed.