IC Netlist Functional Block Identification via Subgraph Growing
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Solution Overview
Problem
Current integrated circuit (IC) analysis systems rely heavily on human expertise to organize and analyze low-level netlists into functional, modular, and hierarchical blocks, which is time-consuming and costly, and existing automated methods lack accuracy and feasibility for high-level abstraction.
Innovation Solution
A probabilistic model combined with partitioning hints, fingerprint matching, and graph matching is used to characterize and analyze IC netlists, enabling the identification of functional blocks and progressive characterization of gate-level netlists by growing sub-graphs and discarding non-matching seeds, thus reducing the need for human intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated methods are used to extract logic from ICs, then productivity is improved, but measurement precision and reliability deteriorate due to lack of accuracy in high-level abstraction
Solution Approach 1:
The patent segments the IC analysis process into distinct phases: seed selection, seed growing, and functional block identification. Each phase operates with specific algorithms and criteria, allowing automated processing while maintaining accuracy through structured decomposition of the overall task.
Solution Approach 2:
The patent performs preliminary characterization of the netlist and pre-processing of data before the main analysis. Reference netlists are pre-characterized and stored in databases, enabling faster and more accurate matching during the automated analysis phase without sacrificing precision.
2Measurement precision
If expert level human effort is used to organize netlists into functional blocks, then measurement precision is improved, but productivity deteriorates due to time consumption and cost
Solution Approach 1:
The system performs self-service through automated algorithms that characterize netlists, select seeds, grow functional blocks, and identify functionalities without requiring expert human intervention. The automated methods use probabilistic models and pattern recognition to achieve results previously requiring human expertise.
Solution Approach 2:
The patent replaces the mechanical process of manual expert analysis with automated computational methods. Algorithms substitute for human experts in organizing netlists, identifying functional blocks, and characterizing circuit functionalities, thereby eliminating time consumption and cost associated with human labor while maintaining or improving accuracy.
3Ease of operation
If existing automated methods use rule-based abstraction, then ease of operation is improved, but measurement precision deteriorates due to lack of feasibility for higher level abstraction
Solution Approach 1:
The patent employs dynamic algorithms that adapt during the analysis process. The seed growing mechanism dynamically expands functional blocks based on matching criteria, and the system adjusts its characterization methods based on the complexity and type of circuit being analyzed, enabling feasible high-level abstraction while maintaining ease of automated operation.
Solution Approach 2:
The system changes parameters during analysis, using different characterization methods and matching criteria at different levels of abstraction. Probabilistic models adjust their parameters based on the data being analyzed, enabling the system to handle both low-level gate-level netlists and high-level functional identification with the same automated framework.
4Measurement precision
If known base library is required for subgraph isomorphism algorithms, then measurement precision is improved, but adaptability deteriorates due to inability to handle modern optimization techniques
Solution Approach 1:
The patent creates a universal system that can handle multiple types of IC designs and netlist formats without requiring a completely known base library. The probabilistic model and pattern recognition algorithms are designed to work with various optimization techniques and synthesis methods used in modern IC design, making the system adaptable while maintaining identification accuracy.
Solution Approach 2:
The system uses feedback mechanisms where the analysis results are continuously refined and compared against reference data. This feedback loop allows the system to adapt to different design styles and optimization techniques, improving both accuracy and versatility by learning from the data being analyzed rather than relying solely on pre-defined libraries.
Data Source
AI summary
The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist.