IC Interconnection Network Route-Error Detection via Redundant Check Codes
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Solution Overview
Problem
Integrated circuits face challenges in detecting faults within their interconnection networks, particularly in ensuring correct data routing and error detection, especially when hardware faults cause misrouting or delays, which can lead to incorrect behavior at destination nodes despite the payload reaching its intended destination.
Innovation Solution
The interconnection network employs route selection circuitry at ingress ports to transmit an actual route vector and an initial error detecting code (EDC) calculated based on a pre-manipulated route vector, allowing for error detection even if the payload reaches the destination but via an incorrect route, using a method that does not require each router to be aware of its position within the network, and utilizing a type of EDC capable of detecting multi-bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detecting codes are transmitted with every data packet, then fault detection capability is improved, but bandwidth consumption and transmission overhead increase
Solution Approach 1:
The patent pre-calculates and stores error detecting codes (EDCs) for all possible route vectors before operation. When a data packet is transmitted, the ingress port selects the pre-computed EDC corresponding to the chosen route vector, avoiding real-time calculation overhead. This preliminary preparation reduces the computational burden during actual data transmission while maintaining comprehensive error detection coverage.
Solution Approach 2:
The patent transmits a copy of the route vector along with the data packet, and the egress port uses this copied route vector to regenerate and verify the EDC. Instead of transmitting the EDC separately for every packet, the system uses the route vector copy to derive the expected EDC at the destination, reducing transmission overhead while maintaining verification capability.
2Measurement precision
If the system verifies route correctness by comparing EDCs at egress ports, then routing accuracy is improved, but processing time and computational overhead increase
Solution Approach 1:
The patent pre-computes and stores error detecting codes for all possible route vectors in lookup tables before the interconnection network operates. During data transmission, the ingress port simply retrieves the appropriate pre-computed EDC based on the selected route vector, avoiding time-consuming real-time calculations. This preliminary preparation significantly reduces verification processing time while maintaining routing accuracy.
Solution Approach 2:
The patent replaces complex real-time EDC calculation mechanisms with simpler lookup table retrieval operations. Instead of performing computational operations to generate EDCs during data transmission, the system uses pre-computed values stored in lookup tables, substituting mechanical computation with faster memory access operations.
3Reliability
If the interconnection network uses complex error detection mechanisms, then fault detection capability is improved, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent divides the error detection function into separate modular components: route selection circuitry at ingress ports, lookup tables for storing pre-computed EDCs, transmission circuitry for sending data packets with route vectors, and verification circuitry at egress ports for comparing EDCs. This segmentation allows each component to be independently designed, implemented, and tested, reducing overall implementation complexity.
Solution Approach 2:
The patent introduces lookup tables as intermediary structures that store pre-computed error detecting codes. These lookup tables act as mediators between the route selection logic and the error verification process, eliminating the need for complex real-time EDC generation logic in the main data path while maintaining comprehensive error detection capability.
4Reliability
If the system transmits pre-manipulated route vectors with data, then error detection coverage is improved, but transmission data volume and bandwidth usage increase
Solution Approach 1:
The patent uses the route vector to serve multiple functions simultaneously: it provides routing information to guide data packets through the network, and it serves as the basis for generating and verifying error detecting codes. This multi-functionality eliminates the need for separate error detection data transmissions, as the route vector itself carries dual purposes, reducing overall transmission data volume while maintaining comprehensive error detection coverage.
Data Source
AI summary
An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.