IC Overlay Correction Using CD Feedback Across Multiple Layers
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Solution Overview
Problem
Advanced integrated-circuit device production processes face alignment errors due to heating cycles, leading to distorted x-coordinate and y-coordinate locations across multiple layers, which increase interconnect resistance and reduce the effectiveness of the devices.
Innovation Solution
A method and system for tracking and correcting alignment errors by measuring dx- and dy-displacement errors per layer, comparing them to planned coordinates, and feeding back corrections to the photolithographic exposure tool to align subsequent layers accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple redistribution layers and via layers are formed through heating cycles, then the integrated-circuit device structure becomes more complex with more interconnect layers, but the x-coordinate and y-coordinate locations become distorted and misaligned from one layer to the next
Solution Approach 1:
The patent applies preliminary action by measuring and recording the overlay alignment status after each heating cycle and curing operation, before proceeding to the next layer formation. This allows the alignment state to be captured and used for subsequent corrections, preventing cumulative distortion from affecting future layers.
Solution Approach 2:
The patent implements feedback by using the measured overlay alignment data from previous layers to adjust and correct the positioning of subsequent layers. The alignment information is fed back to the photolithographic exposure tool to compensate for distortion, ensuring accurate feature placement across multiple layers.
2Device complexity
If the number of process layers increases to twelve redistribution layers and twelve via layers, then the interconnect structure becomes more sophisticated, but the cumulative overlay error increases and features become increasingly misaligned
Solution Approach 1:
The patent performs preliminary measurements of overlay alignment after each heating cycle and curing operation, capturing the alignment state before the next layer is formed. This preliminary action allows correction to be applied in advance, preventing cumulative errors from degrading reliability.
Solution Approach 2:
The patent uses feedback mechanisms where measured overlay alignment data from previous layers is fed back to the photolithographic exposure tool to correct positioning in subsequent layers. This continuous feedback loop maintains feature alignment accuracy even as the number of process layers increases.
3Ease of manufacture
If heating cycles are performed during curing operations, then the ABF layers and other materials are properly cured, but the x-coordinate and y-coordinate locations are distorted
Solution Approach 1:
The patent performs preliminary measurements of overlay alignment immediately after heating cycles and curing operations, capturing the distortion state before the next processing step. This allows the curing process to be completed while preserving knowledge of the resulting alignment state for subsequent corrections.
Solution Approach 2:
The patent implements feedback by using the measured overlay distortion data from cured layers to adjust and correct the positioning in subsequent layers. The distortion information is fed back to the photolithographic exposure tool to compensate for the heating-cycle-induced misalignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Minimizes interconnect resistance and ensures that integrated-circuit devices meet tolerance levels by reducing cumulative overlay errors, allowing for effective fabrication of subsequent layers.
Implementation Method 1
exposing a first plurality of features on a first layer of a substrate with the exposing being performed by a photolithographic exposure tool
Data Source
AI summary
Various examples described herein include a correction for a layer-to-layer or substrate-to-substrate overlay alignment based upon feedback from critical-dimension (CD) measurements of locations of various features that are to be formed on subsequently formed layers of a substrate with regard to locations of similar features on previously formed layers. The layer-to-layer or substrate-to-substrate overlay-alignment feedback can be enhanced by determining positions of multiple ones of the features on each of the formed layers with respect to the first layer in the stack. Further, the layer-to-layer or substrate-to-substrate overlay-alignment feedback can be enhanced by determining positions of multiple ones of the features on each of the formed layers with respect to the previously formed layer. Overlay-alignment errors may be sent back to a photolithographic exposure tool. An accumulated overlay error can be flagged. Other techniques and methods are also disclosed.