IC Overlay Mark Structure for Via-to-Metal Alignment Accuracy
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Solution Overview
Problem
The challenge in integrated circuit manufacturing is the misalignment of conductive vias and metal lines due to decreasing alignment tolerances, leading to nonfunctioning circuits, as the size of transistor features and metal interconnect structures decrease, which results in poor diffraction-based overlay measurement signals and subsequent misalignment of metal tracks with conductive vias.
Innovation Solution
An enhanced overlay mark region is introduced, featuring semiconductor fins, dummy gate structures, and gratings of first and second metal structures, which ensures a sufficient height for second metal structures after CMP, enabling strong diffraction-based overlay measurements for proper alignment of subsequent masks and reliable formation of metal lines in contact with conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor features and metal interconnect structures are decreased in size to increase computing power, then the number of transistors per area increases, but alignment tolerances decrease leading to misalignment of conductive vias and metal lines
Solution Approach 1:
The patent applies preliminary action by forming a dummy gate structure before the actual gate structure to establish a reference for alignment. The dummy gate is formed in advance to create a visible target for overlay measurements, enabling subsequent alignment corrections before the critical gate patterning step. This preliminary structure serves as a foundation for achieving precise alignment in later processing steps despite reduced tolerance margins.
Solution Approach 2:
The patent introduces an intermediary overlay target structure consisting of the dummy gate and associated alignment marks. This intermediary structure mediates between the lithography system and the final device features by providing a measurable reference that translates coarse alignment into fine alignment. The overlay target acts as a buffer that allows measurement and correction of alignment errors without directly affecting the critical dimensions of the transistors themselves.
2Manufacturing precision
If alignment tolerances are decreased to accommodate smaller features, then manufacturing precision requirements increase, but diffraction-based overlay measurement signals become weaker leading to poor measurement accuracy
Solution Approach 1:
The patent applies local quality by creating a specialized overlay mark region with distinct structural characteristics different from the active device regions. The overlay mark region contains larger, more widely spaced features specifically optimized for diffraction-based measurement, while the active device regions maintain their scaled-down dimensions for high-density integration. This localized differentiation allows strong measurement signals in the overlay region without compromising the density requirements in the device regions.
Solution Approach 2:
The patent transitions from measuring alignment in the lateral plane only to incorporating vertical dimension information through multi-layer overlay marks. The overlay structure includes features at different heights and layers that create stronger diffraction signals by utilizing the third dimension. This dimensional expansion provides additional measurement pathways and enhances signal strength without increasing lateral feature sizes that would reduce device density.
3Measurement precision
If the height of second metal structures is insufficient after CMP, then overlay measurements cannot be performed accurately, but increasing height requires additional processing steps
Solution Approach 1:
The patent merges the overlay mark formation process with the existing metal interconnect formation process. The first and second metal structures that would normally be separate processing steps are combined into a single continuous metal layer that serves both as the interconnect structure and as the overlay measurement target. This consolidation eliminates the need for separate overlay mark formation steps while ensuring sufficient height for accurate measurements through the combined structure.
Solution Approach 2:
The patent creates a universal metal structure that simultaneously serves multiple functions: it acts as the electrical interconnect for device operation, provides the structural foundation for subsequent processing, and serves as the diffraction-based overlay measurement target. This multi-functional design eliminates the need for dedicated overlay marks that would require separate processing, as the same metal structures fulfill all three roles without additional fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves alignment accuracy and increases wafer yields by providing a strong diffraction-based overlay measurement signal, ensuring that metal lines are correctly formed in contact with conductive vias, resulting in better functioning integrated circuits.
Implementation Method 1
the second metal structures form a diffraction grating that provides a strong signal for diffraction-based overlay measurements
Data Source
AI summary
An integrated circuit includes a device region and an overlay mark region. The device region includes a plurality of stacked channels of a transistor, a source/drain region of the transistor, a source/drain contact of a first material on the source/drain region, and a conductive via of a second material in contact with the source/drain contact. The overlay mark region includes a first diffraction grating of first metal structures of the first material and a second first diffraction grating of second metal structures above of the second material above and offset from the first metal structures.