Integrated Circuit Package Layout for Thin High-Density 3DICs
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and reduced thickness in 3DICs due to complex packaging requirements and the need for additional circuit boards and bumps, which increase manufacturing costs and time.
Innovation Solution
A method of forming an integrated circuit package with a package structure on a carrier substrate, including integrated circuits, encapsulants, redistribution layers, and conductive pillars, where the redistribution layers are directly formed over the package structure, eliminating the need for additional circuit boards and bumps, and allowing for high-density integration and efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional packaging methods with additional circuit boards and bumps are used, then electrical connections can be established, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the circuit board function and bump interconnect function into a single integrated redistribution layer structure. This redistribution layer is formed directly on the package substrate and provides both mechanical support and electrical connection functions, eliminating the need for separate circuit boards and bumps, thereby reducing device complexity while maintaining reliable electrical connections
Solution Approach 2:
The patent extracts and eliminates the unnecessary intermediate circuit board and bump components from the traditional packaging architecture. By directly forming redistribution layers on the package substrate, the design removes redundant elements that add complexity without contributing essential functionality, achieving simpler packaging while preserving electrical connectivity
2Reliability
If traditional packaging with additional circuit boards and bumps is used, then electrical connections are established, but manufacturing time and cost increase
Solution Approach 1:
The patent performs preliminary action by forming the redistribution layers directly on the package substrate during the packaging process itself, before final assembly. This eliminates the need for subsequent steps of attaching separate circuit boards and bumps, reducing manufacturing time and process steps while ensuring reliable electrical connections are established early in the fabrication sequence
Solution Approach 2:
By combining the circuit board and bump functions into a single integrated redistribution layer structure that is formed in-place, the patent reduces the number of manufacturing steps. This merging eliminates sequential operations of attaching separate components, thereby reducing manufacturing time and cost while maintaining electrical connection reliability
3Productivity
If chip stacking is used to improve integration density, then faster speeds and higher bandwidth are achieved, but package thickness and manufacturing complexity increase
Solution Approach 1:
The patent transitions from vertical stacking (3D IC) to a planar redistribution approach by forming multiple redistribution layers on the package substrate. This dimensional change allows high integration density to be achieved through lateral expansion and multi-layer routing rather than vertical stacking, reducing package thickness while maintaining productivity and bandwidth through efficient in-plane interconnect design
4Productivity
If chip stacking is used to improve integration density, then faster speeds are achieved, but device complexity increases
Solution Approach 1:
The patent replaces complex vertical stacking architecture with a planar multi-layer redistribution approach. By forming redistribution layers directly on the package substrate, the design achieves high integration density through lateral routing and multi-layer interconnects rather than vertical chip stacking, thereby reducing packaging structure complexity while maintaining high productivity and performance
Data Source
AI summary
An integrated circuit package includes a package structure including a plurality of first dies, a second redistribution structure, a second die and a second encapsulant. The package structure includes the first dies, a first encapsulant encapsulating the first dies, a first redistribution structure over the first encapsulant and a plurality of conductive pillars over the first redistribution structure. The second redistribution structure is disposed over the package structure, and electrically connected to the package structure through the conductive pillars. The second die is disposed between the conductive pillars and electrically connected to the second redistribution structure, wherein a first surface of the second die is substantially flush with a surface of the first redistribution structure and a second surface opposite to the first surface of the second die is substantially flush with a surface of the second redistribution structure. The second encapsulant encapsulates the conductive pillars and the second die.