IC Package Asymmetric Encapsulation for Planar Solder Mounting
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Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in providing comprehensive protection to integrated circuit (IC) chips, especially in terms of mechanical shock resistance and scalability for different chip sizes, as they typically only encapsulate the top and bottom faces of the chips, leaving the sides exposed and requiring separate hardware for varying chip sizes.
Innovation Solution
The proposed solution involves encapsulating the sides and both faces of the IC chip with a material that forms a planar surface, allowing solder balls to be mounted on the exposed ends of pillar bumps, and using a release film during molding to prevent encapsulant material from covering the bump tops, enabling the same hardware to be used for different chip sizes and enhancing protection and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods are used that only encapsulate top and bottom faces, then manufacturing simplicity is maintained, but mechanical protection and reliability are insufficient
Solution Approach 1:
The patent applies asymmetry by creating a non-uniform encapsulation structure where the encapsulant extends different heights on different sides of the chip. Specifically, the encapsulant forms a first height on sides with pillar bumps and a second height on opposite sides, creating an asymmetric profile that provides targeted protection while maintaining manufacturing simplicity through a single molding process.
Solution Approach 2:
The patent transitions from conventional 2D face-only encapsulation to 3D multi-level encapsulation by extending the encapsulant material to different heights on different sides of the chip. This dimensional change creates a stepped or asymmetric profile that provides comprehensive mechanical protection while allowing solder balls to be mounted on exposed pillar bump tops.
2Adaptability or versatility
If separate hardware is used for different chip sizes, then manufacturing precision is maintained, but device complexity and cost increase
Solution Approach 1:
The patent achieves universality by designing a single encapsulation mold and molding process that can accommodate multiple chip sizes. The asymmetric encapsulation profile and release film technique work consistently across different chip dimensions, eliminating the need for separate hardware configurations for different chip sizes while maintaining manufacturing precision.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the release film positioning and molding parameters to accommodate different chip sizes within the same hardware system. The mold cavity dimensions and release film placement can be varied to suit different chip footprints, allowing one piece of equipment to handle multiple chip sizes through parameter adjustment rather than requiring dedicated hardware for each size.
3Reliability
If encapsulant material covers pillar bump tops, then comprehensive protection is achieved, but solder ball mounting becomes difficult
Solution Approach 1:
The patent applies preliminary anti-action by using a release film to prevent the encapsulant material from covering the pillar bump tops during the molding process. The release film is strategically positioned to block the encapsulant flow at critical areas while allowing it to protect other surfaces, thereby preserving solder ball mounting accessibility before the encapsulation is complete.
Solution Approach 2:
The release film serves as an intermediary element between the encapsulant material and the pillar bump tops. It temporarily occupies space during molding to prevent encapsulant intrusion onto the bump surfaces, then is removed afterward to expose clean pillar bump tops for solder ball mounting, while the encapsulant provides comprehensive protection to all other exposed surfaces.
Data Source
AI summary
A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free from encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.