IC Package Bonding with Bevel-Cleaned Dielectric Sidewalls
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving efficient and cost-effective packaging techniques for semiconductor dies as the demand for smaller and more integrated electronic devices increases, necessitating innovative methods to reduce manufacturing cycle times and costs while improving bonding performance.
Innovation Solution
A method involving the attachment of semiconductor devices to a carrier substrate, encapsulation in a dielectric layer, and a bevel clean process to expose sidewalls for oxide layer formation, followed by dielectric-to-dielectric and metal-to-metal bonding, reduces the number of fabrication steps and enhances bonding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional packaging techniques are used for semiconductor dies, then manufacturing processes are well-established, but manufacturing cycle times are long and costs are high
Solution Approach 1:
The patent combines multiple packaging operations into a single integrated process. Specifically, it bonds multiple semiconductor dies to a carrier substrate in one step, forms encapsulant material around all dies simultaneously, and performs bevel cleaning on multiple edges in parallel. This merging of sequential operations into concurrent processes directly reduces manufacturing cycle time while managing complexity through systematic integration.
Solution Approach 2:
The patent performs preliminary bonding of semiconductor dies to the carrier substrate before final encapsulation. The dies are positioned and bonded in advance, allowing subsequent encapsulant formation and bevel cleaning to proceed efficiently. This preliminary arrangement of components enables faster overall manufacturing by avoiding repositioning or rework in later stages.
2Ease of manufacture
If conventional bonding methods are used, then process reliability is maintained, but the number of fabrication steps increases manufacturing costs
Solution Approach 1:
The patent merges die bonding and encapsulation into a single integrated process flow. By bonding multiple dies to the carrier substrate and then forming encapsulant material around them in sequence without intermediate handling, the process reduces the total number of fabrication steps and associated costs. The bonding performance is maintained through controlled application of the encapsulant material that serves both as adhesive and protective coating.
Solution Approach 2:
The encapsulant material performs multiple functions simultaneously: it bonds the semiconductor dies to the carrier substrate, provides mechanical protection, and creates favorable edge topographies. This multi-functionality eliminates the need for separate bonding agents and protective coatings, reducing material costs and process steps while maintaining reliable bonding performance.
3Reliability
If edge portions are not cleaned, then manufacturing steps are reduced, but bonding performance deteriorates due to unfavorable edge topographies
Solution Approach 1:
The patent performs bevel cleaning on the edges of the encapsulant material and carrier substrate before final bonding operations. This preliminary removal of excess material creates favorable edge topographies that enhance bonding performance in subsequent steps. By addressing edge quality early in the process, the patent ensures reliable bonding without requiring complex corrective measures later.
Solution Approach 2:
The patent applies selective bevel cleaning only to the edge portions of the encapsulant material and carrier substrate where bonding will occur, rather than processing the entire structure. This localized treatment creates optimal bonding surfaces at critical locations while minimizing unnecessary processing elsewhere, maintaining reliability without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing cycle times, lowers costs, and improves bonding performance by creating favorable edge topographies for semiconductor devices, facilitating efficient integration into 3D integrated chip packages.
Implementation Method 1
performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate
Implementation Method 2
depositing an oxide layer on the outer sidewalls of the carrier substrate
Implementation Method 3
bonding a wafer to the first dielectric layer and the first bonding layer, where the wafer includes a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate, and where bonding the wafer to the first dielectric layer includes forming a dielectric-to-dielectric bond between the first dielectric layer and the second dielectric layer
Implementation Method 4
bonding the wafer to the first bonding layer includes forming a metal-to-metal bond between first conductive connectors of the wafer and second conductive connectors of the integrated circuit die
Data Source
AI summary
A method includes bonding an integrated circuit die to a carrier substrate, forming a gap-filling dielectric around the integrated circuit die and along the edge of the carrier substrate, performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate, after performing the bevel clean process, depositing a first bonding layer on the gap-filling dielectric and the integrated circuit die, forming a first dielectric layer on an outer sidewall of the first bonding layer, an outer sidewall of the gap-filling dielectric, and the first outer sidewall of the carrier substrate; and bonding a wafer to the first dielectric layer and the first bonding layer, wherein the wafer comprises a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate.