IC Package Buffer Layer for Encapsulation Edge Stress Relief
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Solution Overview
Problem
The challenge of bonding integrated circuit chips directly onto a substrate is exacerbated by the increased density and corresponding decrease in area, leading to stress and potential damage at the edges of the integrated circuit devices during encapsulation due to materials with high Young's modulus and coefficient of thermal expansion.
Innovation Solution
The integration of stress buffer layers made of a stress reduction material around the integrated circuit devices before encapsulation, which are formed of a polymer material with specific properties to buffer stress at the outer edges, thereby protecting the devices and improving yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuit chips with increased density and decreased area are bonded directly onto a substrate, then integration density is improved, but stress and potential damage at the edges of the integrated circuit devices during encapsulation occurs
Solution Approach 1:
An interposer is introduced as an intermediary component between the integrated circuit chip and the substrate. The interposer redistributes the ball contact areas from the chip to a larger area, thereby reducing stress concentration at the chip edges during encapsulation and preventing potential damage while maintaining high integration density.
Solution Approach 2:
The patent changes the physical parameters of the bonding interface by using an interposer with a larger area than the chip. This area transformation distributes the mechanical stress over a broader region, reducing the stress intensity at critical edge locations during the encapsulation process.
2Strength
If materials with high Young's modulus and coefficient of thermal expansion are used for encapsulation, then structural strength is improved, but stress at the outer edges of integrated circuit devices increases
Solution Approach 1:
The patent applies different material properties to different regions of the package structure. The interposer is positioned specifically at the chip edges where stress concentration occurs, providing localized stress relief. This allows the use of high-strength encapsulant materials in the bulk while protecting the vulnerable edge regions through the interposer's stress-distributing geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress buffer layers effectively mitigate stress from encapsulant expansion, preventing damage to the integrated circuit devices and wafer, enhancing the yield and reliability of the integrated circuit packages.
Implementation Method 1
forming a stress buffer layer around the integrated circuit device, the stress buffer layer including a stress reduction material
Data Source
AI summary
In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.