IC Package Bump Pad Compensation for CTE Mismatch
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Solution Overview
Problem
The challenge in manufacturing integrated circuit packages with larger area dies is achieving precise alignment and thermal bonding between solder bumps and bump pads due to significant differences in the coefficient of thermal expansion between the die and substrate, leading to misalignment and potential cracking during thermal cycling.
Innovation Solution
A method that calculates a shrinkage factor to adjust the location of bump pads on the substrate, ensuring alignment with solder bumps at room temperature, thereby maintaining bond joint integrity during thermal cycling by compensating for the thermal expansion mismatch between the die and substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger area dies are used to accommodate higher transistor densities, then the transistor device density is improved, but the alignment precision between solder bumps and bump pads deteriorates due to thermal expansion mismatch
Solution Approach 1:
The invention applies preliminary action by pre-calculating and pre-positioning bump pads at compensated locations on the substrate before the reflow process. The bump pad locations are adjusted based on predicted thermal expansion differences, so that when thermal cycling occurs, the solder bumps and bump pads remain aligned. This proactive compensation prevents misalignment issues before they occur during manufacturing.
Solution Approach 2:
The invention changes the positional parameters of bump pads on the substrate to compensate for thermal expansion mismatch. By adjusting the location coordinates of bump pads relative to where solder bumps will be placed, the design accounts for differential thermal expansion between the die and substrate materials, ensuring alignment is maintained across temperature variations.
2Adaptability or versatility
If the coefficient of thermal expansion difference between die and substrate is large, then the adaptability to different material combinations is improved, but the bond joint reliability deteriorates due to misalignment and cracking during thermal cycling
Solution Approach 1:
The invention directly addresses thermal expansion by designing bump pad locations that compensate for the differential thermal expansion between die and substrate materials. The bump pads are positioned at offset locations calculated based on the known CTE differences, allowing the bond joints to remain aligned during thermal cycling even when using materials with significantly different expansion coefficients.
Solution Approach 2:
The invention applies preliminary anti-action by pre-compensating for the harmful effects of thermal expansion mismatch. Before thermal cycling occurs, the bump pad locations are adjusted to counteract the expected misalignment, creating a pre-positioned compensation that prevents bonding issues during subsequent thermal processes.
3Quantity of substance
If solder bumps are positioned at corner regions of the die, then the connection density is improved, but the alignment precision deteriorates due to greater thermal displacement at corners during reflow
Solution Approach 1:
The invention applies local quality by implementing location-specific compensation for bump pad positioning. Corner regions, which experience greater thermal displacement, receive different positional compensation adjustments compared to center regions. Each bump pad location is individually calculated based on its specific position on the substrate, allowing optimal alignment compensation tailored to local thermal expansion characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures that solder bump-bump pad pairs remain aligned and form robust bond joints capable of withstanding thermal cycling tests without cracking, enhancing the reliability of integrated circuit packages, especially for larger area dies with high thermal expansion ratios.
Implementation Method 1
differences in the thermal properties of the die and IC package take on added importance... coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1
Data Source
AI summary
An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.