IC Package Cavity and Top Layer for Thermal Management
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Solution Overview
Problem
Existing IC packaging techniques, such as the chip-last approach, are not suitable for all chip types, particularly those with back-side contacts and high heat dissipation requirements, as they fail to provide adequate thermal management and electrical connectivity.
Innovation Solution
An integrated circuit package with a cavity formed in the package module, allowing for the placement of chips with back-side contacts and the application of a thermally conductive top layer that facilitates heat spreading and electrical connectivity, using materials like copper and metal foils, and optionally a heat sink or metal foil layer for enhanced thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a chip-last approach is used with standard packaging, then manufacturing flexibility is improved, but thermal management capability deteriorates for high-power chips
Solution Approach 1:
The patent introduces a vertical dimension for thermal management by placing a heat sink directly underneath the chip on the substrate, creating a thermal conduction path through the substrate thickness. This dimensional approach allows heat to be conducted away vertically from the chip's back side contact, resolving the thermal management limitation of standard chip-last packaging while preserving manufacturing flexibility.
Solution Approach 2:
The substrate serves as a thermal intermediary between the chip and the heat sink. By designing the substrate with appropriate thermal conduction properties and thickness, it mediates the heat flow from the chip's back side contact to the heat sink, enabling effective thermal management in the chip-last packaging approach.
2Adaptability or versatility
If a cavity is formed on the top-side of the package module, then chip placement flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The cavity is formed in the package module before chip placement, allowing the chip to be positioned and connected to exposed circuit interconnections without requiring subsequent complex routing or reconfiguration. This preliminary formation of the cavity simplifies the overall manufacturing process despite the additional step, as it enables direct connection of the chip contacts to the pre-positioned interconnections.
3Reliability
If circuit interconnections are exposed at the bottom of the cavity, then electrical connectivity is improved, but package module complexity increases
Solution Approach 1:
The circuit interconnections are extracted from the embedded layers and exposed at the bottom of the cavity, allowing direct electrical connection to the chip's front side contacts. This extraction eliminates the need for complex through-substrate vias or additional connection layers, simplifying the package structure while ensuring reliable electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a versatile packaging method that accommodates a wide range of chip types, ensuring effective heat dissipation and electrical connectivity, thereby improving the performance and reliability of power and high-performance logic chips.
Implementation Method 1
The top layer may have thermally conductive properties facilitating heat spreading
Implementation Method 2
The top layer may be sputtered metal
Data Source
AI summary
An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.