IC Package Conductive Cavities for Vertical Embedded Components
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Solution Overview
Problem
Traditional package substrates face challenges in maximizing surface area for integrated circuit components, leading to increased z-height and potential warpage, which affects power integrity and I/O density, especially in thin core or coreless substrates.
Innovation Solution
Incorporating a conductive element with cavities that house components vertically, allowing for increased surface area utilization and reduced footprint, while maintaining electrical connectivity to the package substrate, thereby enhancing power integrity and I/O density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If components are disposed on the face of the package substrate, then the surface area for components is increased, but the z-height increases and warpage occurs
Solution Approach 1:
The patent transitions from planar component placement on the substrate face to vertical embedding within the substrate thickness. Cavities are formed inside the package substrate to house components in the z-dimension, allowing high-density component integration without increasing the substrate's footprint or causing warpage from excessive surface mounting
2Length of stationary object
If the package substrate is made thinner to reduce z-height, then the overall package height is reduced, but power integrity deteriorates due to longer inductance loops
Solution Approach 1:
By embedding components vertically within the substrate thickness rather than mounting them on the surface, the patent shortens the inductance loops for power delivery. The conductive element extends through the substrate to provide direct electrical connection to embedded components, reducing the loop area and improving power integrity even in thin-package designs
3Ease of manufacture
If traditional planar routing is used, then manufacturing is simple, but I/O density is limited by available surface real estate
Solution Approach 1:
The patent utilizes the vertical dimension by forming cavities within the substrate thickness to house components. This three-dimensional integration approach dramatically increases I/O density by allowing multiple signal paths and component connections within the substrate volume rather than being constrained to the two-dimensional surface area
Solution Approach 2:
Components are nested within cavities formed inside the package substrate. The conductive element is embedded within the substrate and extends into these cavities to provide electrical connections to the nested components, creating a compact integrated structure that maximizes I/O density
Data Source
AI summary
Disclosed herein are integrated circuit (IC) structures with a conductive element coupled to a first surface of a package substrate, where the conductive element has cavities for embedding components and the embedded components are electrically connected to the conductive element, as well as related apparatuses and methods. In some embodiments, embedded components have one terminal end, which may be positioned vertically, with the terminal end facing into the cavity, and coupled to the conductive element. In some embodiments, embedded components have two terminal ends, which may be positioned vertically with one terminal end coupled to the conductive element and the other terminal end coupled to the package substrate. In some embodiments, embedded components include passive devices, such as capacitors, resistors, and inductors. In some embodiments, a conductive element is a stiffener.