Integrated Circuit Package Cutouts to Reduce Parasitic Capacitance
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Solution Overview
Problem
High parasitic capacitance between metal layers in integrated circuit packages limits the maximum operating frequency, particularly in high-speed serializer/deserializer devices, causing signal waveform distortion and reduced circuit performance.
Innovation Solution
Forming cutouts in the additional electrically conductive layers that completely surround the contact pads to avoid overlap and reduce parasitic capacitance between the contact pads and nearby metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If metal layers are placed close together to increase integration density, then device complexity is reduced and integration is improved, but parasitic capacitance increases causing signal distortion and frequency limitations
Solution Approach 1:
The patent extracts or removes the harmful metal layer material from specific areas by creating cutouts in the additional electrically conductive layer. These cutouts are positioned to completely surround the contact pads, removing the source of parasitic capacitance while preserving the metal layers in other areas for signal routing and power distribution.
Solution Approach 2:
The patent applies local quality by creating non-uniform metal layer structures - specifically, cutouts are formed only in areas surrounding contact pads where parasitic capacitance is harmful, while metal layers are maintained in other areas where they provide useful functions. This localized modification reduces parasitic capacitance without compromising overall device functionality.
2Reliability
If metal layers overlap contact pads to provide comprehensive grounding and power distribution, then electrical connectivity is improved, but parasitic capacitance between metal layers and contact pads increases
Solution Approach 1:
The harmful overlapping metal material is extracted by forming cutouts that completely surround contact pads. This removal eliminates the parasitic capacitance interface between metal layers and contact pads while preserving metal layer connectivity in regions that do not overlap with contact pads.
Solution Approach 2:
The metal layer is segmented into regions - areas with cutouts surrounding contact pads where parasitic capacitance must be minimized, and areas without cutouts where continuous metal coverage provides electrical connectivity. This segmentation allows simultaneous optimization of both connectivity and parasitic reduction.
Data Source
AI summary
An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.