IC Package Die Sidewalls for Gap-Fill Delamination Resistance

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving reliable packaging of integrated circuit dies due to delamination risks associated with gap-fill dielectrics, particularly because existing dicing processes do not consistently produce smooth, vertical sidewalls, which can lead to stress and cracking in the dies.

Innovation Solution

The use of a plasma dicing process to singulate integrated circuit dies and inactive dies, resulting in substantially vertical, smooth, continuous sidewalls, which reduces the risk of delamination during packaging by ensuring better coverage and adhesion of gap-fill dielectrics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional dicing processes are used to singulate integrated circuit dies, then the dicing process is simple and fast, but the sidewalls are not smooth or vertical, leading to delamination risks of gap-fill dielectric

Engineering Contradiction:
Improvedelamination resistanceVSAvoiddicing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces conventional mechanical dicing methods with a plasma-based process. The plasma etching process creates smooth, vertical sidewalls on the integrated circuit dies through controlled chemical reactions, eliminating the mechanical stress and uneven surfaces that cause delamination in traditional mechanical dicing methods.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the physical and chemical parameters of the dicing process by using plasma treatment. The plasma process modifies the surface properties and creates specific sidewall geometries (smooth and vertical) that prevent gap-fill dielectric delamination, addressing the reliability issue through parameter optimization.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If plasma dicing process is used to singulate integrated circuit dies, then smooth vertical sidewalls are achieved reducing delamination risk, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvesidewall smoothness and verticalityVSAvoidmanufacturing process simplicity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent substitutes mechanical dicing with plasma-based singulation. This replacement achieves superior sidewall quality (smooth and vertical) through controlled plasma etching, directly addressing the manufacturing precision requirement despite the increased process complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The plasma dicing process is performed as a preliminary step before packaging, creating the ideal sidewall conditions in advance. This preliminary action ensures that subsequent gap-fill dielectric application occurs on optimally prepared surfaces, preventing delamination issues before they arise.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of integrated circuit packages by minimizing delamination risks and improving the uniformity and completeness of gap-fill dielectric coverage, thereby increasing the package's overall reliability and performance.

Implementation Method 1

The integrated circuit dies and the inactive dies are singulated by a plasma dicing process prior to being packaged in the integrated circuit package

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS20240112924A1Integrated circuit packages and methods
Publication Date: 2024.04.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240112924A1 patent drawing
  • US20240112924A1 patent drawing
  • US20240112924A1 patent drawing

AI summary

An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.