IC Package Dual Connectivity via Vertical Interconnects
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Solution Overview
Problem
The increasing demand for miniaturization in integrated circuit packages poses challenges in achieving low-cost manufacturing, improved yield, and reliability, particularly in providing high I/O density and connectivity while managing fine pitch connections and mounting complexities on shrinking form factors.
Innovation Solution
The integrated circuit package system incorporates a die-attach paddle, terminal pads, and external interconnects, where the terminal pads are exposed on one side and the external interconnects extend below the encapsulation, allowing for dual connectivity options and reducing the aggressive pitch requirements, enabling attachment to both additional integrated circuit devices and system levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package size is reduced to achieve miniaturization, then the portability is improved, but the I/O density increases and manufacturing complexity worsens
Solution Approach 1:
The patent introduces a vertical dimension by extending external interconnects below the encapsulation body, allowing I/O connections to be made from both the top surface (terminal pads) and bottom surface (external interconnects). This multi-directional connectivity approach increases effective I/O capacity without increasing the horizontal footprint of the package, thus maintaining miniaturization while managing I/O density requirements.
2Quantity of substance
If the I/O pitch is reduced to increase connectivity, then the number of I/O is improved, but the manufacturing precision requirements worsen
Solution Approach 1:
The patent divides the connectivity function into two separate segments: terminal pads on the top surface and external interconnects extending from the bottom surface. This segmentation allows each connection type to be optimized independently, with terminal pads handling certain I/O and external interconnects handling others, thereby increasing total I/O capacity without requiring uniformly reduced pitch across the entire package perimeter.
Solution Approach 2:
By utilizing the vertical dimension below the encapsulation for external interconnects, the patent effectively adds a third dimension to the I/O layout. This allows connections to be distributed in three-dimensional space rather than constrained to a two-dimensional perimeter, increasing I/O capacity without proportionally reducing pitch requirements.
3Length of stationary object
If the package profile is reduced to achieve thinner design, then the form factor is improved, but the connectivity options are limited
Solution Approach 1:
The patent extends external interconnects vertically below the encapsulation body, utilizing the z-dimension to provide additional connectivity pathways. This allows the package to maintain a thin profile while offering multiple connection points: terminal pads on the top surface for one set of connections and external interconnects from the bottom surface for another set, thereby preserving versatility despite reduced thickness.
4Quantity of substance
If the lead pitch is reduced to increase I/O density, then the connectivity is improved, but the reliability of connections worsens
Solution Approach 1:
The patent segments the connection interface into two distinct types: terminal pads on the top surface and external interconnects extending from the bottom surface. This segmentation distributes the I/O load across different physical locations and connection methods, allowing each connection type to be optimized for its specific function and reducing the stress and reliability risks associated with uniformly high-density fine-pitch connections.
Data Source
AI summary
An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side at an opposing side to the first side, surrounding the integrated circuit die with the terminal pad exposed at the first side and the external interconnect extending below the second side.