Integrated Circuit Package with Partially Exposed Die Recess

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Solution Overview

Problem

Current multi-chip packages face challenges in achieving high integrated circuit density, reliability, and cost-effectiveness due to limitations in testing individual integrated circuits before assembly, potential damage during assembly, and contamination issues during encapsulation, leading to assembly defects and increased manufacturing costs.

Innovation Solution

A mountable integrated circuit package system where an integrated circuit die is partially exposed within a recess of the package encapsulation, connected via internal interconnects to a package carrier, allowing for flexible mounting and reduced substrate needs, thereby improving testing and assembly processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional multi-chip packages are used with complete encapsulation, then protection and structural integrity are improved, but individual integrated circuit testing before assembly becomes impossible and assembly defects increase

Engineering Contradiction:
Improveassembly reliabilityVSAvoidtesting process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The encapsulation is segmented to create a recess that exposes a portion of the integrated circuit die, allowing the die to be divided into two functional zones: the exposed bonding pads area for testing and mounting, and the encapsulated area for protection. This segmentation enables both testing access and structural protection simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The recess is formed in the encapsulation before the integrated circuit die is mounted, allowing testing and quality verification to be performed on individual dies before they are assembled into the final multi-chip package. This preliminary testing action prevents assembly of defective components.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If vertically stacked integrated circuits are used to increase density, then integrated circuit density is improved, but testing and failure mode identification become more difficult and substrate damage risk increases

Engineering Contradiction:
Improveintegrated circuit densityVSAvoidtesting difficulty
Core Design Contradiction:
Quantity of substanceVSDifficulty of detecting and measuring

Solution Approach 1:

The recess creates a horizontal testing interface on the vertical stack, allowing testing to occur at the bonding pad level rather than requiring disassembly of the vertical stack. This dimensional change in testing access maintains high density while enabling quality verification.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Object-affected harmful factors

If complete encapsulation is used to protect integrated circuits, then protection is improved, but contamination during encapsulation process increases and manufacturing costs rise

Engineering Contradiction:
Improveprotection from contaminationVSAvoidmanufacturing ease
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

Instead of complete encapsulation, only the necessary portions of the integrated circuit die are encapsulated—the recess exposes the bonding pads area. This partial encapsulation action reduces contamination risk during the encapsulation process while still providing protection for the circuit elements.

Inventive Principle:
Principle #16Partial or excessive action

4Quantity of substance

If more integrated circuits are mounted on a single substrate to increase density, then integrated circuit density is improved, but substrate real estate limitations and assembly complexity increase

Engineering Contradiction:
Improveintegrated circuit densityVSAvoidassembly complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The recess structure serves multiple functions simultaneously: it provides testing access, defines the mounting interface for the die, enables quality verification, and maintains structural integrity. This multi-functionality reduces assembly complexity despite high density requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8536692B2Mountable integrated circuit package system with mountable integrated circuit die
Publication Date: 2013.09.17 STATS CHIPPAC LTD
  • US8536692B2 patent drawing
  • US8536692B2 patent drawing
  • US8536692B2 patent drawing

AI summary

A mountable integrated circuit package system includes: mounting an integrated circuit die over a package carrier; connecting a first internal interconnect between the integrated circuit die and the package carrier; and forming a package encapsulation over the package carrier and the first internal interconnect, with the integrated circuit die partially exposed within a recess of the package encapsulation.