IC Package with Exposed Interconnects and Shoulder Bonding

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Solution Overview

Problem

Current integrated circuit package systems face challenges in achieving low-cost manufacturing, improved yield, and reliability while maintaining miniaturization and performance, particularly in portable devices, where conventional packages are complex and costly, and multi-chip solutions have not fully addressed these needs.

Innovation Solution

A mountable integrated circuit package system is introduced, featuring an inner package with a first external interconnect having a shoulder, an intraconnect connecting a second external interconnect to the shoulder, and an outer encapsulation that partially exposes these interconnects on the top and bottom sides, allowing flexible routing of electrical connections and reducing the need for costly wire bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional package configurations with lead frames and wire bonds are used, then electrical connections can be established, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidpackage construction complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the lead frame and wire bond components from the package structure. Instead, it uses direct bonding of bonding pads on the semiconductor die to external interconnects that are integrated into the package substrate, thereby simplifying the package construction while maintaining reliable electrical connections.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the functions of the lead frame, wire bonds, and external interconnects into a single integrated structure. The external interconnects are directly formed on the package substrate and bonded to the die, combining multiple components into one unified system that reduces complexity.

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If multi-chip packages are used to increase density, then integrated circuit density improves, but manufacturing cost and complexity increase

Engineering Contradiction:
Improveintegrated circuit densityVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from planar multi-chip packaging to a three-dimensional stacked configuration. Multiple semiconductor dies are stacked vertically and bonded to each other through the package substrate, utilizing the vertical dimension to achieve high density without increasing the package footprint or manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Volume of moving object

If package size is reduced for miniaturization, then product size decreases, but external interconnect access becomes difficult

Engineering Contradiction:
Improvepackage sizeVSAvoidexternal interconnect access
Core Design Contradiction:
Volume of moving objectVSEase of operation

Solution Approach 1:

The package substrate serves multiple functions simultaneously: it provides mechanical support for the stacked dies, acts as an electrical interconnection network between layers, and provides external access points for electrical connections. This multi-functionality allows compact packaging while maintaining ease of external interconnect access through the substrate's external terminals.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7785929B2Mountable integrated circuit package system with exposed external interconnects
Publication Date: 2010.08.31 STATS CHIPPAC LTD
  • US7785929B2 patent drawing
  • US7785929B2 patent drawing
  • US7785929B2 patent drawing

AI summary

The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.