IC Package Lead Array with Non-Horizontal Profile for Thermal Management

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Solution Overview

Problem

Current integrated circuit packaging technologies face challenges in achieving smaller footprints, higher reliability, and lower costs due to issues with clock rates, EMI radiation, thermal loads, and assembly reliability, while also increasing complexity and error risks during manufacturing.

Innovation Solution

The development of an integrated circuit packaging system with a lead array having an innermost space and leads with unique profiles, where the innermost lead has a non-horizontal side and the middle lead has a consistent profile, along with a package encapsulation that includes a sealing filler to improve thermal performance and prevent mold bleeding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If current packaging technologies are used to achieve smaller footprints, then device size is reduced, but thermal loads and EMI radiation increase

Engineering Contradiction:
Improvepackage footprintVSAvoidthermal loads
Core Design Contradiction:
Area of moving objectVSTemperature

Solution Approach 1:

The lead array is segmented into multiple leads with different profiles (innermost lead with non-horizontal side, middle leads with consistent profile). This segmentation allows different regions of the package to handle thermal and EMI challenges differently, with the innermost lead configuration providing enhanced thermal pathways while maintaining compact footprint.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The innermost lead is given a unique non-horizontal side profile while middle leads have consistent profiles. This local differentiation optimizes thermal management at the critical innermost region where the integrated circuit is placed, allowing improved heat dissipation precisely where needed without increasing overall package size.

Inventive Principle:
Principle #3Local quality

2Reliability

If packaging complexity is increased to improve reliability, then assembly reliability improves, but manufacturing error risk increases

Engineering Contradiction:
Improveassembly reliabilityVSAvoidpackaging complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The innermost lead is designed with an asymmetric non-horizontal side profile while middle leads maintain symmetric consistent profiles. This controlled asymmetry provides enhanced mechanical interlocking and thermal pathways for improved reliability, while the regularity of middle leads keeps manufacturing complexity manageable through standardized processes.

Inventive Principle:
Principle #4Asymmetry

3Ease of manufacture

If production costs are reduced by simplifying manufacturing, then cost decreases, but manufacturing precision may be compromised

Engineering Contradiction:
Improveproduction costVSAvoidlead profile precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies full precision manufacturing only to the critical innermost lead with its unique non-horizontal profile, while middle leads use simpler consistent profiles that require less precision. This partial application of high-precision manufacturing reduces overall production costs while maintaining sufficient precision for reliable assembly.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8957509B2Integrated circuit packaging system with thermal emission and method of manufacture thereof
Publication Date: 2015.02.17 STATS CHIPPAC LTD
  • US8957509B2 patent drawing
  • US8957509B2 patent drawing
  • US8957509B2 patent drawing

AI summary

A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.