IC Package Metal Wall and Backside Layer for Heat Dissipation
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Solution Overview
Problem
As the trend in integrated circuit development focuses on increasing integration density, there is a need to shrink the package size of integrated circuit chips while improving thermal dissipation performance, which existing packaging structures have not adequately addressed.
Innovation Solution
The proposed IC package structure features a panel-shaped array of package units with continuous metal walls surrounding each unit, incorporating a panel-shaped metal layer bonded to the backside of the package units for enhanced thermal conductivity and EMI protection, achieved through electroplating and adhesive materials, allowing for better heat dissipation and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the package size of integrated circuit chips is shrunk to increase integration density, then the integration density is improved, but the thermal dissipation performance deteriorates
Solution Approach 1:
The patent introduces a three-dimensional stacked package structure where multiple IC chips are vertically arranged and connected via through-silicon vias (TSVs). This vertical stacking approach transitions from traditional two-dimensional planar packaging to three-dimensional spatial packaging, thereby increasing integration density without compromising thermal dissipation. The vertical architecture enables heat to be conducted away through multiple pathways including the substrate and interlayer structures, effectively resolving the thermal management challenge associated with high-density packaging.
Solution Approach 2:
The patent divides the package structure into multiple independent layers or stacks, each containing IC chips, TSVs, and interconnect structures. This segmentation allows for modular thermal management where heat can be dissipated locally at each stack level rather than accumulating in a single large package. The segmented architecture enables independent optimization of thermal pathways for each module while maintaining high overall integration density.
2Quantity of substance
If more integrated circuits are integrated on smaller circuit boards, then the integration density is improved, but the thermal management becomes more difficult
Solution Approach 1:
The patent employs a universal substrate structure that serves multiple functions simultaneously: mechanical support for stacked IC chips, electrical interconnection through TSVs, and thermal conduction pathway. This multi-functional substrate design simplifies thermal management by integrating heat dissipation capabilities into the existing packaging infrastructure rather than requiring separate thermal management systems, thereby reducing overall device complexity while maintaining high integration density.
3Quantity of substance
If the package size is reduced, then the integration density is improved, but the electromagnetic interference protection is compromised
Solution Approach 1:
The patent implements a nested shielding structure where conductive shielding layers are integrated within the vertical stack of IC chips and interconnect structures. These shielding layers are positioned between adjacent functional blocks to contain electromagnetic fields locally. The nested architecture enables EMI protection without increasing the overall package footprint, as the shielding elements are embedded within the existing three-dimensional structure rather than adding external layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces package size, enhances thermal dissipation performance, and improves electromagnetic interference protection, addressing the challenges of increased integration density and thermal management in integrated circuit packaging.
Implementation Method 1
achieved through electroplating and adhesive materials
Implementation Method 2
formed on entire back side of the IC package structure and bonded to the metal wall of each package unit, wherein the back side of the IC package structure refers to the side to which the back surface of each IC chip/IC die is facing
Data Source
AI summary
An IC package structure including an array of package units formed into a panel-shaped package units array. Each package unit has a continuous and closed metal wall surrounding the periphery of the package unit and at least one IC chip/IC die disposed in the package unit, and wherein each IC chip/IC die has a top surface and a back surface opposite to the top surface. A panel-shaped metal layer corresponding to the panel-shaped package units array can be formed on entire back side of the IC package structure and bonded to the metal wall of each package unit, wherein the back side of the IC package structure refers to the side to which the back surface of each IC chip/IC die is facing.