Integrated Circuit Package with Metalized Back-Side Thermal Management

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Solution Overview

Problem

Existing integrated circuit packaging techniques, such as the chip-last approach, are not suitable for all chip types, particularly those with back-side contacts and high heat dissipation requirements, as they fail to provide adequate thermal management and electrical connectivity.

Innovation Solution

A package module is fabricated using successive build-up layers with a cavity on the top-side, where a metalized back-side of the chip is attached to a metallic layer, which covers the back-side and top-side of the package module, establishing electrical and thermal connections, and can include features like high-temperature attachment, diffusion soldering, and thermally conductive materials for heat spreading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a chip-last approach is used for packaging, then the packaging process can accommodate standard chips, but it fails to provide adequate thermal management and electrical connectivity for power chips and high-performance logic chips with back-side contacts

Engineering Contradiction:

Improvepackaging compatibilityVSAvoidthermal management

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent inverts the conventional chip-last approach by attaching the chip to the metallic layer before placing it in the cavity, rather than placing the chip first and then attaching components. This inversion enables proper thermal and electrical connectivity for back-side contact chips while maintaining packaging versatility

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The metallic layer serves multiple functions simultaneously: it provides electrical connectivity through the back-side contact, acts as a thermal management solution for heat dissipation, and enables mechanical attachment of the chip. This multi-functionality resolves the contradiction by making a single structure capable of handling both standard and high-performance chips

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a chip-last approach is used for packaging, then the packaging process can accommodate standard chips, but it fails to provide adequate electrical connectivity for chips with back-side contacts

Engineering Contradiction:

Improvepackaging compatibilityVSAvoidelectrical connectivity

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The metallic layer acts as an intermediary between the chip's back-side contact and the package module's circuit interconnections. It provides a dedicated electrical pathway that ensures reliable connectivity while allowing the package to accommodate various chip types with different contact configurations

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the packaging of a wide range of chip types, including power and high-performance logic chips, by providing effective electrical connectivity and thermal management, enhancing heat dissipation and operational efficiency.

Implementation Method 1

Attaching the metalized back-side of the chip onto the metallic layer may be done with a diffusion soldering process

Methodology Applied

Scientific EffectDiffusion soldering: Diffusion Welding

Implementation Method 2

The metallic layer may have thermally conductive properties facilitating heat spreading

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS9105562B2Integrated circuit package and packaging methods

Publication Date: 2015.08.11 INFINEON TECHNOLOGIES AG

AI summary

An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and coupling the metallic layer that is attached to the chip onto the top-side of the package module.