IC Package Configuration with Mold Compound Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The demand for smaller form factors and higher density integrated circuit (IC) packages poses a challenge in existing packaging techniques, as they struggle to accommodate shrinking IC dimensions and provide efficient interconnects for stacked components.
Innovation Solution
The proposed solution involves an IC package configuration that includes a substrate with a semiconductor die or interposer, where one or more interconnect structures are formed on the second surface, encapsulated by a mold compound with vias to facilitate coupling with another component, allowing for various configurations such as wire-bond, flip-chip, and dual flip-chip configurations, along with redistribution layers to enhance electrical and thermal pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional packaging configurations are used, then manufacturing and assembly are simpler, but the package size cannot be reduced and density is limited
Solution Approach 1:
The patent transitions from traditional planar packaging to three-dimensional stacked packaging, where multiple semiconductor dies are vertically stacked and interconnected through vias in the substrate. This dimensional change enables significant reduction in package footprint while accommodating multiple functional layers, directly resolving the contradiction between smaller package size and increased complexity.
Solution Approach 2:
The patent implements nested packaging by placing one semiconductor die within or adjacent to another in a stacked configuration, with smaller components nested within the vertical space occupied by larger ones. This nesting approach maximizes space utilization and achieves high-density packaging without proportionally increasing overall package volume.
2Quantity of substance
If IC structures are shrunk to smaller dimensions for higher density, then package density improves, but existing packaging techniques struggle to accommodate shrinking dimensions
Solution Approach 1:
The patent divides the packaging system into modular segments including individual semiconductor dies, substrate layers with integrated vias, and interconnect structures. Each segment can be manufactured and tested independently before assembly, making the fabrication of high-density stacked packages more manageable and scalable despite the complexity of achieving small dimensions.
3Quantity of substance
If stacked component configurations are implemented, then higher density is achieved, but interconnect structures become more complex
Solution Approach 1:
The substrate acts as an intermediary element that integrates multiple vias and interconnect structures, providing a centralized platform for routing signals between stacked dies. This intermediary approach consolidates the complexity of interconnections into a manageable substrate layer rather than requiring complex direct interconnections between each die pair.
Data Source
AI summary
Embodiments of the present disclosure provide a substrate, one of either a semiconductor die or an interposer disposed on the substrate, the semiconductor die or the interposer having a first surface attached to the substrate and a second surface that is opposite to the first surface, one or more interconnect structures formed on the second surface of the semiconductor die or the interposer, a mold compound formed to substantially encapsulate the semiconductor die or the interposer, and one or more vias formed in the mold compound to facilitate coupling the one or more interconnect structures with another component. Other embodiments may be described and/or claimed.