IC Package Substrate Pad Structure for Reduced Die Clearance

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Solution Overview

Problem

The challenge in integrated circuit (IC) package design is to reduce the die-substrate clearance to minimize the height of the IC package while maintaining effective electrical interfacing and mechanical support.

Innovation Solution

The solution involves incorporating a reduced area, additional metal pad(s) coupled to metal interconnect(s) on the substrate, which allows for a solder joint to be formed with a die interconnect, thereby controlling the clearance between the die and the substrate by adjusting the solder amount or die interconnect length.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a standard metal pad is used to couple the die to the substrate, then reliable electrical connection is achieved, but the die-substrate clearance cannot be reduced sufficiently

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoiddie-substrate clearance
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The metal pad is segmented into two distinct pads: a first metal pad with larger cross-sectional area for mechanical support and electrical connection, and a second metal pad with reduced cross-sectional area for controlling solder flow and minimizing clearance. This segmentation allows each pad to serve its specific function optimally.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the pad structure are given different properties: the first metal pad has larger area for strength and electrical connection, while the second metal pad has reduced area specifically at the location where solder contact occurs, creating local quality variation that controls solder flow and clearance.

Inventive Principle:
Principle #3Local quality

2Reliability

If solder amount is increased to ensure reliable joint formation, then connection reliability improves, but die-substrate clearance reduction is compromised

Engineering Contradiction:
Improvesolder joint reliabilityVSAvoiddie-substrate clearance
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The cross-sectional area parameter of the metal pad is changed by introducing a second pad with reduced area. This parameter change controls the solder flow characteristics, allowing sufficient solder for reliable joint formation while limiting excess solder that would increase clearance.

Inventive Principle:
Principle #35Parameter changes

3Length of stationary object

If the metal pad cross-sectional area is reduced to minimize clearance, then die-substrate clearance is reduced, but electrical connection reliability may be compromised

Engineering Contradiction:
Improvedie-substrate clearanceVSAvoidelectrical connection reliability
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The pad structure is segmented into two pads with different areas. The first pad maintains larger area for electrical connection reliability, while the second pad has reduced area for clearance control, thus resolving the contradiction through functional segmentation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The two metal pads are merged into a single integrated pad structure that combines both functions: the first pad provides electrical connection and mechanical support, while the second pad provides clearance control. The merged structure achieves both objectives simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the die-substrate clearance, thereby lowering the overall height of the IC package, while ensuring reliable electrical connections and mechanical stability.

Implementation Method 1

A solder joint(s) is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS20250192099A1Integrated circuit(IC) package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce die-substrate clearance
Publication Date: 2025.06.12 QUALCOMM INC
  • US20250192099A1 patent drawing
  • US20250192099A1 patent drawing
  • US20250192099A1 patent drawing

AI summary

Integrated circuit package having a substrate employing reduced area, added metal pad(s) to metal interconnect(s) to reduce a die to a substrate clearance and related fabrication methods are disclosed. The IC package includes die interconnects coupled to first metal pad(s) of respective metal interconnects of a metallization layer of the substrate to provide support and signal routing paths. To reduce clearance between the die and the substrate and consequently the height of the IC package, a second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is coupled to the first metal pad(s). Solder is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate. When the solder is heated to form the solder joint, the solder flows along the reduced cross-sectional area of the second, additional metal pad(s).