Electroplated IC Package Pads Without Plating Tails
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Solution Overview
Problem
In integrated circuit chip packaging, the presence of plating tails on electroplated pads degrades signal integrity due to increased signal noise, particularly in high-frequency circuits, as they can interfere with input and output signals.
Innovation Solution
A method is developed to form electroplated pads on packaging substrates without plating tails by depositing a conductive seed layer, applying a mask to cover the plating tail portion, performing electroplating on the pad portion, and then removing the mask and plating tail portion, resulting in pads with a reliable surface finish.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroplating is performed on electrical connection pads to prevent oxidation, then the reliability of solder joints is improved, but plating tails are formed which degrade signal integrity
Solution Approach 1:
The patent applies the extraction principle by removing the harmful plating tails from the packaging substrate after electroplating the pads. The method involves forming plating tails during electroplating to enable complete pad coverage, then selectively removing these tails through etching or mechanical means, leaving only the necessary pad area with protective plating. This extracts the harmful signal noise element while preserving the beneficial oxidation protection.
Solution Approach 2:
The patent segments the electroplating process into distinct phases: first forming plating tails that extend beyond pad boundaries to ensure complete coverage, then selectively removing the excess tail portions. This segmentation allows the process to achieve both complete pad protection and clean signal paths by separating the protective function from the harmful signal interference.
2Ease of manufacture
If plating tails are used to facilitate electroplating of multiple pads, then the ease of manufacture is improved, but the device complexity increases due to signal interference issues
Solution Approach 1:
The patent simplifies the manufacturing process by using plating tails during electroplating to achieve complete pad coverage, then extracting/removing these tails afterward. This approach maintains ease of manufacture during the plating phase while eliminating the complexity of signal interference in the final product.
Solution Approach 2:
The patent applies preliminary action by forming plating tails before the actual pad plating to ensure complete coverage is achieved easily, then removing these tails afterward. This preliminary structure enables simple electroplating execution while the subsequent removal eliminates signal interference complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signal integrity and improves the performance of integrated circuit chips by eliminating signal degradation caused by plating tails, leading to more robust solder joints and reliable connections in package-on-package designs.
Implementation Method 1
performing an electro-plating process on the packaging substrate to deposit a metallic layer on the pad portion
Data Source
AI summary
An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the electrical connection pad. The electrical connection pad includes an electroplated surface finish layer, but does not include an electrical trace configured as a plating tail. Because the electrical connection pad is free of a plating tail, signal degradation caused by the presence of plating tails in the integrated circuit package is avoided.