IC Package with Embedded Passive Structures for Signal Integrity
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Solution Overview
Problem
The reduction of overall package size in wafer level fan-out packages is hindered by the arrangement of passive components near conductive lines, leading to increased cross-talk and signal interference, which degrades reliability and assembly complexity.
Innovation Solution
The method involves encapsulating integrated circuit dies with a molding compound and forming passive components over it, with capacitor structures surrounding the dies, and forming conductive vias to connect these components to metal routing layers on a redistribution wafer, allowing for improved electrical connectivity and reduced interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If passive components are arranged in proximity to conductive lines in the wafer area, then the overall package size can be reduced, but cross-talk and signal interference increase, degrading package reliability and performance
Solution Approach 1:
The patent transitions passive component placement from the wafer plane (2D) to the vertical dimension above the wafer (3D). Passive components are positioned in the molding compound above the conductive lines, utilizing the Z-axis dimension to achieve spatial separation. This dimensional transition allows compact wafer area while maintaining electrical isolation and reducing cross-talk between active and passive elements.
Solution Approach 2:
The molding compound serves as an intermediary medium that physically separates and electrically isolates passive components from conductive lines on the wafer. The molding compound encapsulates the wafer and provides a non-conductive environment, allowing passive components to be positioned in proximity without direct electrical contact, thus reducing signal interference while maintaining compact packaging.
2Device complexity
If passive components are arranged in proximity to conductive lines, then integration density increases, but signal interference and cross-talk increase, making assembly more difficult
Solution Approach 1:
By positioning passive components in the vertical dimension above the wafer rather than on the wafer plane, the patent achieves high integration density without increasing lateral complexity. This 3D arrangement simplifies the manufacturing process by eliminating the need for precise lateral alignment between passive components and conductive lines, as connections are established through vertical vias in the molding compound.
Solution Approach 2:
The patent segments the packaging structure into distinct functional layers: the wafer layer containing active circuitry and conductive lines, and the molding compound layer containing passive components. This segmentation allows independent optimization and manufacturing of each layer, simplifying the overall assembly process while maintaining high integration density through vertical interconnection.
3Area of stationary object
If passive components are formed on or embedded in the wafer substrate, then package area is reduced, but cross-talk and signal interference increase, degrading performance
Solution Approach 1:
The patent relocates passive components from the wafer plane to the vertical space above the wafer, utilizing the third dimension to achieve area reduction without compromising electrical isolation. This spatial repositioning maintains compact package area while the molding compound provides natural shielding and isolation, eliminating cross-talk and signal interference issues associated with planar integration.
Solution Approach 2:
The molding compound acts as an intermediary that provides both mechanical support and electrical isolation for passive components positioned above the wafer. This intermediary layer enables area-efficient packaging by allowing passive components to be positioned in the vertical space without direct contact with conductive lines, thereby preventing signal interference while maintaining compact footprint.
Data Source
AI summary
An integrated circuit package with embedded passive structures may include first and second integrated circuit dies that are surrounded by capacitor structures. A molding compound is deposited to encapsulate the integrated circuit dies and the capacitor structures. The molding compound is then attached to a redistribution wafer, in which the integrated circuit dies and the capacitor structures are electrically connected to metal routing layers of the redistribution wafer. A conductive layer is subsequently formed over the first integrated circuit die in the molding compound. The conductive layer is made up of additional metal routing layers and inductor structures. The integrated circuit package may further include a group of conductive vias that is formed in the molding compound. Each conductive via has a first end contacting the metal routing layers of the distribution wafer, and a second end contacting the conductive layer.