Parasitic Analysis of IC Packages and PCBs Using Pin Clustering

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Solution Overview

Problem

Current methods for simulating integrated circuit (IC) package and printed circuit board (PCB) designs are inefficient due to the complexity of extracting parasitic values for thousands of pins, which can take weeks and may not be feasible under turnaround time constraints, especially as designs become more complex and smaller in size.

Innovation Solution

A preprocessing method that identifies and clusters 'hotspot' pins with high parasitic values and groups other pins based on proximity and common nets, allowing for reduced complexity in parasitic value calculations while maintaining precision by performing parasitic analysis on both individual hotspots and clusters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional parasitic extraction methods are used on all pins, then measurement precision is maintained, but loss of time increases significantly

Engineering Contradiction:
Improveparasitic value extraction precisionVSAvoidextraction time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent segments pins into two categories: hotspots requiring detailed parasitic extraction and non-hotspots that can use simplified extraction. This segmentation allows selective application of computational resources, maintaining precision for critical pins while reducing overall extraction time by processing non-critical pins with simplified methods.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different extraction quality levels to different regions of the design. Hotspot pins receive full-precision parasitic extraction, while non-hotspot pins use simplified extraction. This local differentiation maintains measurement precision where needed while reducing time loss in less critical areas.

Inventive Principle:
Principle #3Local quality

2Productivity

If the number of pins is reduced for processing, then productivity increases, but measurement precision may deteriorate

Engineering Contradiction:
Improveprocessing speedVSAvoidparasitic value accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary identification of hotspot pins before the main parasitic extraction process. By pre-identifying which pins require detailed analysis, the system can prioritize computational resources appropriately, maintaining productivity through efficient resource allocation while preserving measurement precision for critical pins.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback from preliminary analysis to guide the main extraction process. The identification of hotspots based on initial assessment feeds into the detailed extraction phase, ensuring that productivity gains from selective processing do not compromise the precision of parasitic values for pins that require high accuracy.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If all pins are analyzed individually, then measurement precision is maintained, but device complexity increases

Engineering Contradiction:
Improveindividual pin analysis accuracyVSAvoidcalculation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the analysis process into individual detailed analysis for hotspots and clustered simplified analysis for non-hotspots. This segmentation reduces device complexity by avoiding individual analysis of all pins, while maintaining measurement precision for critical hotspot pins through selective individual analysis.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges non-hotspot pins into clusters for collective processing, reducing calculation complexity. By combining these pins into groups that can be analyzed together, the system reduces the overall computational burden while maintaining sufficient precision for non-critical pins, reserving individual analysis only for hotspots.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11354483B1Parasitic representation of large scale IC packages and boards
Publication Date: 2022.06.07 ANSYS INC
  • US11354483B1 patent drawing
  • US11354483B1 patent drawing
  • US11354483B1 patent drawing

AI summary

Improved parasitic analysis of a design of an electrical circuit (e.g. a PCB coupled to an IC package) can use a first parasitic analysis to identify a first set of pins having excessive parasitic values (“hotspots” in the design) and then identify a second set of pins that do not have excessive parasitic values. The pins in the second set can be clustered (e.g. using a grid of cells) to reduce a model size for calculations in a second parasitic analysis, and the pins in the first set can be analyzed in the second parasitic analysis either individually or in clusters of similar pins with excessive parasitic values.