Leadless IC Package Fabrication With Fully Plated Side Flanks
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Solution Overview
Problem
Leadless semiconductor packages face challenges in achieving full plating of side flanks, which are non-wettable due to untreated copper surfaces, making solder joint inspection difficult and reducing solder strength, especially in dual/quad flat no-lead (DFN/QFN) packages.
Innovation Solution
A method involving a conductive substrate, such as conductive tape or glue, is applied to the bottom side of leadless packages to facilitate electro-plating of side walls, followed by precise cutting to singulate the packages, ensuring all side flanks are fully plated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electro-plating is used on leadless packages, then the copper surface is plated, but the side flanks remain non-wettable due to untreated surfaces
Solution Approach 1:
The method applies preliminary action by performing side flank exposure through cutting before the electro-plating process. This ensures that the side flanks are properly prepared and accessible for plating, allowing complete coverage rather than leaving untreated surfaces. The cutting step creates fresh copper surfaces that are then immediately plated, guaranteeing wettable side flanks.
Solution Approach 2:
The process segments the manufacturing steps into distinct phases: first exposing side flanks through cutting, then applying electro-plating separately. This segmentation allows each step to be optimized independently - the cutting ensures proper exposure while the plating ensures complete coverage, resolving the contradiction between plating coverage and surface treatment.
2Object-affected harmful factors
If side flanks are left flush with mould compound for protection, then environmental protection is improved, but solder wicking is prevented and inspection becomes difficult
Solution Approach 1:
The invention applies local quality by creating a stepped configuration where only specific areas (side flanks) are exposed and plated, while other areas remain protected by mould compound. This localized exposure allows solder to wet the side flanks for inspection and strength, while the rest of the package maintains environmental protection. The selective plating of side flanks provides both protection and inspectability.
3Productivity
If multiple flat no-lead packages are manufactured together and singulated, then production efficiency is improved, but side portions are not coated with solder wettable material
Solution Approach 1:
The method performs preliminary cutting to expose side flanks before the electro-plating process in batch manufacturing. This preliminary action ensures that when multiple packages are processed together, all side flanks are properly exposed and will receive uniform plating coverage, maintaining both productivity and plating precision.
Solution Approach 2:
The manufacturing process is segmented into exposure and plating phases, allowing batch processing of multiple packages while ensuring each package's side flanks are properly treated. This segmentation maintains production efficiency through batch handling while guaranteeing precise plating coverage on all side portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables full plating of side flanks, allowing for effective solder fillet formation and visual inspection, enhancing solder strength and reliability in leadless packages.
Implementation Method 1
performing the process of electro-plating of the lead frame, thereby obtaining plating on the areas not covered by the conductive substrate
Data Source
Figure 1
Figure 2A~2E
Figure 3
AI summary
The present disclosure discloses a method of fabricating a semiconductor integrated circuits package with solder wettable plating, comprising the following steps: providing an array of leadless packages placed on singulation tape, wherein the array comprises a lead frame, each having contact pads at the underside and an encapsulation layer in which the integrated circuits are encapsulated; adjoining a conductive substrate to the array of leadless packages at the bottom side, thereby electrically connecting all contact pads of the array; performing a first set of parallel cuts, extending fully through the lead frame and encapsulation layer, and defining rows of the array, thereby exposing the side walls of the lead frames; performing the process of electro-plating of the lead frame, thereby obtaining plating on the areas not covered by the conductive substrate; removing the conductive substrate from the bottom of the packages; performing a second series of parallel cuts, angled with respect to the first series of parallel cuts, the cuts extending fully through the lead frame and the encapsulation layer, and separating the array into columns thereby singulating the packages between the edge portions. The step of performing a second series of parallel cuts is performed after removing the conductive substrate (for DFN packages) or after the step of performing the first set of parallel cuts and before plating step (for QFN packages).