IC Package with Hybrid-Bonded Power Gating for Dense I/O
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Solution Overview
Problem
The increasing density of input/output (I/O) pads on integrated circuit dies complicates die packaging, especially as semiconductor technologies evolve and more functions are integrated into smaller dies, necessitating improved packaging technologies for greater parallel processing capabilities.
Innovation Solution
The integration of processor devices and power gating devices, where the power gating devices are formed with larger active devices than the processor devices, utilizing switch transistors of a large technology node for power delivery, and employing hybrid bonding without adhesive materials to reduce power consumption and increase interconnection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of I/O pads on integrated circuit dies is increased to accommodate more functions, then the number of I/O pads increases, but the area available for I/O pads decreases
Solution Approach 1:
The patent employs fan-out packaging technology that redistributes I/O pads from the die surface to a larger package substrate area. This dimensional expansion allows the same number of I/O pads to be accommodated on a larger effective area, resolving the contradiction between increasing I/O pad quantity and available die area.
Solution Approach 2:
The packaging structure is segmented into multiple functional layers including the die, interconnect structure, and package substrate. This segmentation allows I/O pads to be redistributed across different spatial planes, effectively increasing the available area for I/O connections without increasing the die footprint.
2Area of moving object
If processor devices are made smaller to increase integration density, then die area decreases, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple functions into an integrated package structure that includes the processor die, power gating devices, and interconnect structures all within a single package. This merging approach allows smaller die sizes while managing complexity through integrated design rather than separate components.
Solution Approach 2:
An interconnect structure serves as an intermediary between the processor die and package substrate, providing redistribution and connection functions. This intermediary layer simplifies the packaging of smaller dies by handling the complexity of I/O routing externally rather than requiring complex on-die routing.
3Loss of energy
If power gating devices use larger active devices for power delivery, then power consumption decreases, but device area increases
Solution Approach 1:
The patent applies different quality standards to different parts of the system: power gating devices use larger active devices optimized for low power consumption, while logic devices use smaller features optimized for high density. This local differentiation allows each component to be optimized for its specific function without compromising overall system area efficiency.
Data Source
AI summary
In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.