3D IC Package With Power Gating Die for Dense I/O Scaling
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Solution Overview
Problem
The increasing density of input/output (I/O) pads on integrated circuit dies, coupled with reduced available area, complicates die packaging and hinders parallel processing capabilities.
Innovation Solution
The integration of processor devices and power gating devices, where power gating devices are formed with larger active devices, utilizing switch transistors of a large technology node for power delivery, and direct bonding techniques to reduce power consumption and improve interconnection performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of I/O pads on integrated circuit dies is increased to accommodate more functions, then the number of I/O pads increases, but the area available for I/O pads decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of I/O pads on the die surface to a three-dimensional fan-out package structure. The I/O pads are redistributed across multiple layers and a larger footprint area, effectively adding vertical and lateral dimensions to the I/O pad layout. This allows significantly more I/O pads to be accommodated without increasing the die area, as pads can be stacked and distributed across the package substrate in three-dimensional space.
Solution Approach 2:
The patent segments the I/O pad distribution into multiple functional layers and regions. The I/O pads are divided and redistributed across different planes of the package substrate, with some pads routed through intermediate layers. This segmentation allows the limited die surface area to be expanded into a multi-layer configuration, effectively increasing the total I/O pad capacity while maintaining a compact die footprint.
2Productivity
If multiple dies are integrated to achieve greater parallel processing capabilities, then processing power increases, but packaging complexity increases
Solution Approach 1:
The patent merges multiple separate die packaging processes into a single integrated fan-out package structure. Multiple dies are co-packaged together on the same package substrate with unified I/O pad redistribution and routing. This consolidation reduces the overall packaging complexity compared to individually packaging each die separately, while still achieving the desired parallel processing capabilities through the multi-die configuration.
Solution Approach 2:
The fan-out package structure serves multiple functions simultaneously: it provides I/O pad redistribution, accommodates multiple dies for parallel processing, enables routing and interconnection, and offers mechanical support. This multi-functional design reduces packaging complexity by eliminating the need for separate structures for each function, as a single integrated package substrate performs all necessary roles.
3Power
If power gating devices with larger active devices are used for power delivery, then power delivery performance improves, but device area increases
Solution Approach 1:
The patent moves the power gating devices from a two-dimensional planar layout on the die surface to a three-dimensional configuration within the fan-out package. The larger active devices are distributed across multiple layers and routed through the package substrate, allowing sufficient power delivery capability without concentrating all power devices in a single planar region. This vertical and lateral distribution reduces the immediate die area requirement while maintaining overall power delivery performance.
Data Source
AI summary
In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.