IC Package Power Island Layout for Low-Parasitic Decoupling

Solution Overview

Problem

Existing integrated circuit packages with backside-mounted decoupling capacitors face challenges in providing an integrated reference plane for high-speed signaling, limiting signaling speeds and throughput due to space constraints and parasitic inductance and resistance.

Innovation Solution

The integrated circuit package design includes decoupling capacitors mounted on the topside of the substrate, with power traces connecting them to the circuit die and forming power islands, which reduces parasitic effects and frees up space for data signal lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If decoupling capacitors are mounted on the backside of the substrate, then space is freed on the front side, but parasitic inductance and resistance increase and integrated reference plane cannot be provided

Engineering Contradiction:

Improveavailable space on substrate front sideVSAvoidparasitic inductance and resistance

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional mounting location of decoupling capacitors from the backside to the front side of the substrate, placing them in close proximity to the circuit die. This inversion reduces parasitic inductance and resistance by shortening current paths and enables integrated reference plane implementation for high-speed signaling.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent applies local quality by creating distinct functional zones: decoupling capacitors are strategically placed near specific circuit die regions requiring power stabilization, and integrated reference planes are formed in specific substrate areas to provide localized electromagnetic shielding and signal reference for high-speed data lines.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If decoupling capacitors are mounted on the backside of the substrate, then manufacturing is simplified, but signaling speed and throughput are limited

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidsignaling speed

Core Design Contradiction:

Ease of manufactureVSSpeed

Solution Approach 1:

The patent inverts the conventional mounting location of decoupling capacitors from the backside to the front side of the substrate, placing them in close proximity to the circuit die. This inversion reduces parasitic inductance and resistance by shortening current paths and enables integrated reference plane implementation for high-speed signaling.

Inventive Principle:

Principle #13The other way round (Inversion)

3Reliability

If decoupling capacitors are mounted on the front side of the substrate near the circuit die, then signal integrity improves and parasitic effects reduce, but space for other components decreases

Engineering Contradiction:

Improvesignal integrityVSAvoidavailable space on substrate

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by creating distinct functional zones: decoupling capacitors are strategically placed near specific circuit die regions requiring power stabilization, and integrated reference planes are formed in specific substrate areas to provide localized electromagnetic shielding and signal reference for high-speed data lines.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements nesting by integrating multiple functions into compact structures: decoupling capacitors are positioned within the footprint area of the substrate in close proximity to the circuit die, and integrated reference planes are formed using the substrate's ground layers, effectively nesting electromagnetic shielding and power decoupling functions within the same spatial envelope.

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances signal integrity and reduces parasitic inductance and resistance, allowing for higher signaling speeds and increased throughput while also lowering manufacturing costs and complexity.

Implementation Method 1

a decoupling capacitor (decap) may be used to improve electrical performance of integrated circuit (IC) packages, e.g., to increase switching speeds by storing a charge from a Vin power supply to sustain Vout

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

the power trace can be part of an electrically conductive power pathway that includes a through-substrate via passing through the substrate

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12347816B2Integrated circuit package with decoupling capacitors

Publication Date: 2025.07.01 NVIDIA CORP

AI summary

IC package including a substrate having a first surface, a circuit die coupled to the first surface of the substrate, a decoupling capacitor coupled to the first surface of the substrate and a power trace coupled to the first surface of the substrate and connected to the circuit die and to the decoupling capacitor. A method of manufacturing an IC package include providing a substrate providing a substrate having a first surface, forming a power trace on the first surface of the substrate, mounting a circuit die on the first surface, where the circuit die is electrically connected to the power trace and mounting a decoupling capacitor on the first surface of the substrate, where the decoupling capacitor is electrically connected to the power trace and to the circuit die.