IC Package Dielectric Stack Layout for Scribe-Line Sawing
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing delamination during the sawing process of integrated circuit dies and achieving uniform step coverage of dielectric layers in the scribe line region, which affects the reliability and efficiency of packaging techniques.
Innovation Solution
Forming a lower subset of dielectric layers only in the scribe line region and removing the upper subset of dielectric layers from the scribe line region, allowing for reduced delamination during sawing while increasing the step coverage of the upper dielectric layers by maintaining a dielectric layer in the scribe line region during the redistribution structure formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If all dielectric layers are formed in the scribe line region, then the step coverage of upper dielectric layers is improved, but delamination occurs during the sawing process
Solution Approach 1:
The dielectric layers are segmented into two subsets based on their location and function: a lower subset formed in the scribe line region to prevent delamination during sawing, and an upper subset removed from the scribe line region to maintain step coverage uniformity. This segmentation allows each subset to serve its specific purpose without causing the adverse effects of the other.
Solution Approach 2:
Different regions of the structure are given different qualities: the lower dielectric layers are present in the scribe line region to provide mechanical support and prevent delamination, while the upper dielectric layers are removed from the scribe line region to ensure uniform step coverage in the active device regions. This local differentiation resolves the contradiction between these two requirements.
2Reliability
If the wafer is sawn in the scribe line region with all dielectric layers present, then delamination is reduced, but the thickness uniformity of dielectric layers deteriorates
Solution Approach 1:
The dielectric layer structure is segmented vertically into lower and upper subsets, and horizontally into scribe line and active region portions. The lower subset extends into the scribe line region to prevent delamination during sawing, while the upper subset is confined to active regions to maintain uniform thickness. This multi-dimensional segmentation resolves the contradiction between delamination resistance and thickness uniformity.
3Manufacturing precision
If dielectric layers are removed from the scribe line region, then thickness uniformity is improved, but delamination occurs during sawing
Solution Approach 1:
The dielectric layers are divided into lower and upper subsets with different spatial extents. The lower subset remains in the scribe line region to prevent delamination, while the upper subset is removed from the scribe line region to maintain thickness uniformity. This segmentation strategy simultaneously achieves both objectives.
Solution Approach 2:
The structure exhibits local quality variations: in active regions, full dielectric layer stacks provide proper electrical isolation and step coverage, while in scribe line regions, only lower dielectric layers remain to prevent delamination without compromising thickness uniformity in active regions. This local differentiation resolves the contradiction.
Data Source
AI summary
Embodiments include a method for forming an integrated circuit package. A first dielectric layer is deposited over a wafer, the first dielectric layer overlapping a package region and a scribe line region of the wafer. A first metallization pattern is formed extending along and through the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern and the first dielectric layer, the second dielectric layer overlapping the package region and the scribe line region. The second dielectric layer is removed from the scribe line region, the second dielectric layer remaining in the package region. After the second dielectric layer is removed from the scribe line region, a second metallization pattern is formed extending along and through the second dielectric layer. The wafer and the first dielectric layer are sawed in the scribe line region.