Multi-Form IC Package with Side Contact Pads for High I/O Density

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Solution Overview

Problem

Conventional IC packages face challenges in increasing I/O interconnect density without significantly increasing production costs, particularly in applications requiring a large number of input/output connections.

Innovation Solution

A multi-form IC package design featuring a substrate with a two-dimensional array of substrate modules, including upper and lower contact pads with a redistribution layer connecting them, combined with a modified lead frame array and encapsulation, allowing for higher I/O density through both contact pads and leads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the density of I/O interconnects is increased to increase chip utility, then the number of input/output nodes increases, but production cost increases

Engineering Contradiction:
Improvenumber of I/O interconnectsVSAvoidproduction cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from conventional two-dimensional I/O interconnect arrangements to a three-dimensional configuration by adding side contact pads that protrude from the sides of the encapsulant. This dimensional change allows additional I/O nodes to be accessed without increasing the planar footprint, thereby increasing I/O density without proportionally increasing production cost

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive interface is segmented into multiple types of contact pads: bottom contact pads for electrical connection and side contact pads that protrude from the encapsulant sides. This segmentation allows different I/O nodes to be accessed through different spatial locations, increasing the total number of I/O interconnects without requiring a uniform increase in interconnect density across the entire package

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conventional package types are used, then manufacturing is straightforward, but I/O interconnect density is limited

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidI/O interconnect density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The package structure serves multiple functions: the bottom contact pads provide electrical connection to the substrate, while the side contact pads provide additional I/O access points. This multi-functional design allows the same package structure to achieve both conventional manufacturing simplicity and enhanced I/O density

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

By adding side contact pads that extend from the vertical sides of the encapsulant, the patent utilizes the third dimension (height/depth) to increase I/O interconnect density without complicating the manufacturing process. This maintains compatibility with conventional packaging techniques while achieving higher I/O capacity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9362212B1Integrated circuit package having side and bottom contact pads
Publication Date: 2016.06.07 CHIP PACKAGING TECH LLC
  • US9362212B1 patent drawing
  • US9362212B1 patent drawing
  • US9362212B1 patent drawing

AI summary

A packaged integrated circuit device includes a substrate module, leads, an IC die having first and second sets of die contact pads, and an encapsulant. The substrate module has upper and lower sets of conductive contacts on its upper and lower surfaces, respectively. The upper set of conductive contacts is electrically connected to the lower set of conductive contacts. The first set of die contact pads is electrically connected to the upper set of conductive contacts. The second set of die contact pads is electrically connected to the leads. Certain embodiments are a multi-form packaged device having both leads and conductive balls supporting different types of external connections, such as BGA and QFN.