IC Package Heat Dissipation Structure With Single-TIM Thermal Path
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving efficient thermal management and cooling for high-density integrated circuits due to limitations in thermal interface materials and 3D packaging technologies, which result in increased thermal resistance and reduced cooling performance.
Innovation Solution
A Chip-on-Wafer-on-Substrate (CoWoS) package structure is developed, featuring a ring surrounding the package component, a molding compound filling spaces between the ring and the component, and a plurality of thermal-conductive metal layers in contact with the component, along with a single application of thermal interface material (TIM) for improved cooling, and optionally, nanowires on the thermal-conductive layers for enhanced heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple applications of thermal interface material (TIM) are used in 3D packaging, then thermal contact between components is improved, but thermal resistance increases and cooling performance deteriorates
Solution Approach 1:
The patent removes the intermediate TIM layer between the molding compound and the heat dissipation structure, extracting the problematic thermal resistance source. By directly bonding the heat dissipation structure to the molding compound, the system eliminates the TIM-related thermal resistance while maintaining thermal contact through the direct bond interface.
Solution Approach 2:
The patent employs a composite heat dissipation structure comprising a heat dissipation plate made of high-thermal-conductivity material (such as copper or aluminum) combined with a heat dissipation fin structure. This composite design creates efficient thermal pathways from the package component through the molding compound to the heat dissipation structure, achieving effective heat transfer without relying on multiple TIM layers.
2Quantity of substance
If 3D packaging with multiple chips is implemented, then integration density is improved, but thermal management becomes more difficult and cooling performance is reduced
Solution Approach 1:
The patent transitions from planar heat dissipation to three-dimensional heat dissipation by implementing a heat dissipation fin structure extending vertically from the heat dissipation plate. This dimensional change provides increased surface area for heat transfer in the vertical dimension, enabling effective cooling of high-density 3D packaged components that generate significant heat in a compact footprint.
Solution Approach 2:
The heat dissipation structure is segmented into distinct functional zones: a heat dissipation plate in direct thermal contact with the molding compound for heat collection, and heat dissipation fins extending outward for heat distribution and dissipation. This segmentation creates optimized thermal pathways that efficiently manage heat from multiple chips packaged in three-dimensional arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces thermal resistance and enhances cooling performance by utilizing a single application of TIM and potentially nanowires, leading to improved heat dissipation and reduced thermal resistance in 3D packaging.
Implementation Method 1
a plurality of thermal-conductive layers over and in physical contact with the molding compound and the package component
Implementation Method 2
A thermal interface material (TIM) is applied to a top surface of the plurality of conductive metal layers
Implementation Method 3
a liquid cooling device (for example, a liquid cooled cold-plate or other suitable device) is thereafter coupled to the plurality of thermal-conductive metal layers
Data Source
AI summary
A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, where the ring surrounds the first die and the interposer, a molding compound disposed between the ring and the first die, where the molding compound is in physical contact with the ring, and a plurality of thermal-conductive layers over and in physical contact with the molding compound and the first die, where the molding compound is disposed between the plurality of thermal-conductive layers and the ring.