IC Package Delay Circuit for Clock-Data Skew Control
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Solution Overview
Problem
As electronic products become smaller, multi-functional, and high-performance, the demand for integrated circuit packages with high data bandwidth increases, leading to reduced data-valid window margins and increased coupling noise, which deteriorates signal integrity.
Innovation Solution
An integrated circuit package with a substrate, semiconductor chips, and an active interposer including a delay circuit to delay clock and data signals, improving the data-valid window and skew between clock and data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data input/output speed is increased to achieve high data bandwidth, then productivity is improved, but the data-valid window margin decreases and signal integrity deteriorates
Solution Approach 1:
The delay circuit performs preliminary adjustment on the clock signal and data signal before they are transmitted between chips. By pre-delaying the signals according to predetermined delay values, the system ensures that signals arrive at the optimal time at the receiving end, maintaining adequate data-valid window margins even at high data rates.
Solution Approach 2:
The system changes the time domain parameters of the signals by introducing controlled delays. The delay circuit adjusts the phase and timing of clock and data signals, transforming their temporal characteristics to compensate for transmission delays and improve signal integrity at high bandwidths.
2Productivity
If data input/output speed is increased, then productivity is improved, but coupling noise increases and deteriorates signal integrity
Solution Approach 1:
The delay circuit performs preliminary synchronization of signals before transmission. By pre-adjusting the timing of clock and data signals, the system minimizes the duration and impact of signal transitions that generate coupling noise, thereby reducing noise interference at high data rates.
3Device complexity
If chips are horizontally spaced apart on the substrate, then device complexity is reduced and manufacturing is simplified, but signal skew between clock and data signals increases
Solution Approach 1:
The delay circuit performs preliminary compensation for the horizontal spacing between chips. By pre-calculating and applying appropriate delay values to signals based on their expected transmission paths, the system compensates for the additional skew introduced by horizontal chip arrangement, ensuring synchronized signal arrival at the receiving chip.
Solution Approach 2:
The system changes the timing parameters of signals to compensate for spatial separation. The delay circuit adjusts the temporal characteristics of clock and data signals, transforming their arrival times to maintain proper synchronization despite horizontal chip spacing.
Data Source
AI summary
An integrated circuit package may include a substrate, a first semiconductor chip disposed on the substrate and configured to output a first clock signal and a first data signal, a delay circuit configured to delay at least one of the first clock signal and the first data signal, and to output a second clock signal and a second data signal based on the first clock signal and the first data signal, and a second semiconductor chip disposed on the substrate to be horizontally spaced apart from the first semiconductor chip and configured to receive the second clock signal and the second data signal.