IC Package Stress Buffer Structure for Delamination Relief
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Solution Overview
Problem
The challenge of integrating semiconductor components into a given area has surpassed the ability to bond an integrated circuit chip directly onto a substrate, leading to stress accumulation and delamination defects in three-dimensional packages.
Innovation Solution
Forming stress relief features, such as shallow recesses and chamfer-shaped corners, in the insulating bonding layer of integrated circuit dies during the dicing process, which are adhered to an underlying interposer using a molding compound, reducing stress and improving bonding integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If integrated circuit chips are directly bonded onto a substrate to increase integration density, then the area occupied by components is reduced, but stress accumulation and delamination defects occur in three-dimensional packages
Solution Approach 1:
The patent divides the bonding interface into multiple stress relief features (recesses and chamfers) distributed across the insulating bonding layer. These segmented features create localized stress distribution points that prevent cumulative stress buildup, thereby maintaining bonding integrity while enabling high-density integration.
Solution Approach 2:
The patent incorporates stress relief features (recesses and chamfers) into the insulating bonding layer before the bonding process. These pre-formed features act as cushioning elements that absorb and distribute thermal and mechanical stresses before they can cause delamination, thus preventing reliability issues in advance.
2Reliability
If stress relief features such as shallow recesses and chamfer-shaped corners are formed in the insulating bonding layer, then stress is reduced and adhesion is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines the formation of stress relief features (recesses and chamfers) with the existing dicing process. By integrating these features into the insulating bonding layer during standard fabrication steps, the patent avoids adding separate manufacturing stages, thus minimizing process complexity while achieving stress reduction.
Solution Approach 2:
The stress relief features are formed during the dicing process itself, which is a preliminary step before bonding. This preliminary action ensures that stress relief structures are already in place before the chip is bonded to the substrate, eliminating the need for additional post-dicing modifications.
3Productivity
If three-dimensional packages with multiple chips are implemented using interposers, then integration density is increased, but stress accumulation leads to delamination defects
Solution Approach 1:
The patent applies stress relief features specifically at the bonding interface regions where stress concentration is most critical. The recesses and chamfers are strategically positioned in the insulating bonding layer to provide localized stress management, maintaining high integration density while protecting vulnerable bonding areas from delamination.
Data Source
AI summary
In an embodiment, a package include an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds. The package further includes an encapsulant over the interposer and surrounding the integrated circuit die. The encapsulant is further disposed between the first insulating bonding layer and the second insulating bonding layer along a line perpendicular to a major surface of the first semiconductor substrate.