IC Package Back-Side TEC Cooling for Dense Chip Integration

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Solution Overview

Problem

The semiconductor industry faces challenges in bonding integrated circuit chips directly onto substrates due to limitations in 2D integration, which hinders the ability to accommodate increased density and heat management, leading to hot spots and thermal inefficiencies.

Innovation Solution

A Chip-on-Wafer-on-Substrate (CoWoS) package structure with enhanced cooling from the back side of the package substrate using a thermoelectric cooling module (TEC) and thermal interface material (TIM) to manage heat and facilitate bonding of multiple semiconductor chips, ensuring efficient thermal management and power delivery without hot spots.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If more semiconductor chips are integrated into a given area to increase density, then integration density is improved, but heat management deteriorates leading to hot spots and thermal inefficiencies

Engineering Contradiction:

Improveintegration densityVSAvoidheat management

Core Design Contradiction:

Quantity of substanceVSTemperature

Solution Approach 1:

The patent transitions from 2D planar integration to 3D vertical stacking by introducing an interposer layer between the substrate and chips. This dimensional change allows chips to be positioned at different heights and enables back-side cooling access, effectively adding a vertical dimension for both integration and thermal management.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer serves as an intermediary component that redistributes ball contacts from the chip to a larger area, providing both electrical interconnection and mechanical support. This intermediary structure enables improved heat dissipation by separating the chip bonding surface from the substrate and allowing cooling mechanisms to access the chip back side.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Quantity of substance

If 3D package structures are used to incorporate multiple chips, then integration density is improved, but device complexity increases

Engineering Contradiction:

Improvenumber of chipsVSAvoidpackage structure

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the package into distinct functional segments: the substrate providing mechanical support and power delivery, the interposer handling signal redistribution and electrical connections, and the chips containing active circuitry. This segmentation allows each component to be optimized independently and simplifies the overall assembly process.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The interposer performs multiple functions simultaneously: it acts as an electrical interconnection layer, a mechanical support structure, and a thermal management interface. This multi-functionality reduces the need for additional specialized components, thereby managing complexity while enabling 3D integration of multiple chips.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Device complexity

If direct bonding of chips to substrate is used, then device complexity is reduced, but thermal management capability deteriorates

Engineering Contradiction:

Improvebonding structureVSAvoidthermal efficiency

Core Design Contradiction:

Device complexityVSTemperature

Solution Approach 1:

Instead of cooling the chip from its bonding surface (front side), the patent inverts the cooling approach by providing thermal management access from the chip's back side. The interposer structure enables cooling mechanisms to contact the chip back surface, reversing the conventional cooling direction and effectively removing heat at its source without interfering with the bonding interface.

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables improved thermal management and temperature control, allowing for a greater number of semiconductor chips to be bonded while preventing heat traps and hot spots, enhancing the overall performance and functionality of the integrated circuit package.

Implementation Method 1

A Chip-on-Wafer-on-Substrate (CoWoS) package structure with enhanced cooling from the back side of the package substrate using a thermoelectric cooling module (TEC)

Methodology Applied

Scientific EffectThermoelectric effect: Peltier Effect

Implementation Method 2

thermal interface material (TIM) to manage heat and facilitate bonding of multiple semiconductor chips

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20250343104A1Integrated circuit packages and methods of forming the same

Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming a package structure, where forming the package structure includes attaching a package component to a front side of a package substrate, where the package component includes a first die, and attaching a second die to a back side of the package substrate, and inserting a portion of the package structure into a first cavity of a fixture, where the fixture includes a thermoelectric cooling (TEC) module that is disposed in a second cavity of the fixture, where the second cavity of the fixture is disposed within a bottom surface of the first cavity, where after inserting the portion of the package structure into the first cavity of the fixture, the second die is in thermal contact with the TEC module, and where the fixture is coupled to a printed circuit board (PCB).