IC Package Redistribution Structure for Stress-Buffered UBM
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Solution Overview
Problem
The semiconductor industry faces challenges in creating smaller and more reliable packaging techniques for semiconductor dies, particularly in buffering mechanical stresses and ensuring high integration density, as existing methods struggle with cracking and delamination in redistribution structures.
Innovation Solution
The formation of under-bump metallurgies (UBMs) with specific height-to-width ratios and thick dielectric layers in redistribution structures to buffer mechanical stresses, increasing the reliability of the redistribution structure during testing and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing packaging techniques are used, then integration density can be achieved, but mechanical stress causes cracking and delamination in redistribution structures
Solution Approach 1:
The patent applies beforehand cushioning by introducing a compliant layer between the redistribution structure and the substrate. This layer is designed to absorb and buffer mechanical stresses before they can propagate through the redistribution structure, preventing cracking and delamination from occurring in the first place during thermal cycling and mechanical loading.
Solution Approach 2:
The patent employs composite materials by creating a multi-layer redistribution structure that combines rigid interconnect layers with a compliant buffer layer. This composite construction allows the structure to simultaneously maintain structural integrity for electrical connections while the compliant layer provides mechanical stress relief, resolving the contradiction between strength and stress resistance.
2Quantity of substance
If smaller feature sizes are used to increase integration density, then more components can be integrated, but mechanical stress concentration increases
Solution Approach 1:
The patent applies segmentation by dividing the redistribution structure into multiple functional layers: rigid interconnect layers for electrical signaling and a separate compliant buffer layer for mechanical stress management. This segmentation allows the system to achieve high integration density through miniaturized interconnects while the buffered layer prevents stress concentration from propagating through the entire structure.
3Reliability
If thicker dielectric layers are used to buffer mechanical stress, then reliability improves, but device height increases
Solution Approach 1:
The patent applies local quality by placing the compliant buffer layer specifically at the interface where mechanical stress concentration occurs, rather than uniformly increasing the thickness of all dielectric layers. This localized approach provides stress buffering functionality where needed while maintaining minimal overall device height, as the compliant layer is positioned precisely at the critical stress interface between the redistribution structure and substrate.
Data Source
AI summary
In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 μm to 30 μm; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.