3D Stacked IC Package with Vertical FETs and Thermal Vias
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Solution Overview
Problem
Designing integrated circuit (IC) packages that meet high power requirements, provide effective heat dissipation, and offer flexible signal routing in a compact form factor, while maintaining efficiency and cost-effectiveness in manufacturing, is a challenge, particularly for small devices like smartphones and tablets.
Innovation Solution
The solution involves an IC package configuration that includes a bottom leadframe, an interposer mounted on the leadframe, a flipchip die attached to the interposer, and a top leadframe electrically connected to the interposer, with a dual leadframe module that incorporates two vertical FETs and passive circuit components, allowing for efficient heat dissipation and flexible signal routing through a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a compact package design is used, then the device size is reduced, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical stacking architecture. Multiple circuit layers are stacked vertically with through-silicon vias (TSVs) providing inter-layer connections, enabling compact packaging while maintaining effective heat dissipation pathways through the vertical dimension.
Solution Approach 2:
The patent implements localized heat dissipation structures including heat sinks positioned at specific high-power regions, thermal vias distributed throughout the package, and thermally conductive materials placed strategically between heat-generating components and heat dissipation paths, allowing efficient heat management in compact volumes.
2Adaptability or versatility
If complex circuits with high power requirements are integrated, then functionality is improved, but heat generation increases
Solution Approach 1:
The patent divides the circuit system into multiple functional layers stacked vertically, with power-intensive components separated from sensitive components. Through-silicon vias segment the interconnection paths, allowing independent optimization of power delivery and signal routing, thereby managing heat generation in high-power circuits while maintaining overall functionality.
Solution Approach 2:
The patent introduces intermediate thermal management structures including thermal interface materials between components and heat sinks, thermal vias as intermediaries conducting heat from active regions, and heat spreaders that mediate heat distribution, enabling complex high-power circuits to function without excessive heat generation.
3Adaptability or versatility
If signal routing flexibility is increased, then circuit design freedom is improved, but package complexity increases
Solution Approach 1:
The patent achieves signal routing flexibility by adding the vertical dimension through multiple stacked layers with through-silicon vias providing inter-layer connections. This three-dimensional routing architecture enables flexible signal paths without increasing lateral package complexity, as routing decisions are distributed across vertical layers rather than requiring complex lateral interconnections.
Data Source
AI summary
A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.