IC Package Via Bonding for Parasitic Reduction
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in minimizing the form factor and electrical parasitics, particularly at higher frequencies, with wire-based interconnections limiting frequency performance and bump-based interconnections being costly and inflexible.
Innovation Solution
The integrated circuit package system employs a substrate with a plated via forming a conductor having a closed end, allowing direct electrical connection of the integrated circuit die to the substrate, reducing parasitics and eliminating the need for additional covering materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire-based interconnection is used to connect chip to carrier, then ease of manufacture and design flexibility are improved, but electrical parasitics increase and frequency performance deteriorates
Solution Approach 1:
The patent extracts the harmful wire loop structure from the interconnection path and replaces it with a direct bonded wire configuration. The wire is bonded directly from chip pad to carrier pad without forming a loop, eliminating the primary source of inductance while maintaining the ease of wire-based manufacturing and design flexibility.
Solution Approach 2:
The patent transitions from a planar wire loop interconnection to a three-dimensional bonded wire structure that passes through a via in the substrate. This dimensional change allows the wire to achieve a shorter electrical path with reduced inductance while maintaining connectivity between chip and carrier.
2Object-affected harmful factors
If bump-based interconnection is used to connect chip to carrier, then electrical parasitics are reduced and frequency performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent introduces a substrate with plated vias as an intermediary structure between the chip and carrier. This substrate provides pre-formed conductive paths that guide the bonded wire from chip pad to carrier pad, achieving low parasitic performance similar to bump-based interconnection while maintaining the simplicity of wire bonding processes.
3Adaptability or versatility
If wire loop interconnection is used, then design flexibility is maintained, but inductance increases and frequency limit is reduced
Solution Approach 1:
The patent removes the wire loop configuration that causes high inductance and replaces it with a direct bonded wire path through the substrate. This extraction of the harmful loop structure maintains design flexibility while enabling operation at higher frequencies by reducing the inductance to minimal levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances electrical performance by providing a shorter interconnection path and reduces costs associated with material coverage, while maintaining design flexibility and structural integrity.
Implementation Method 1
forming a conductor in the opening provided in the substrate
Implementation Method 2
bonding in via
Data Source
AI summary
An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.