Integrated Circuit Package Via Formation
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the physical size of semiconductor devices while maintaining performance and efficiency, particularly in packaging techniques for miniaturized integrated circuits, as traditional methods are costly and time-consuming, and there is a need for more innovative approaches to integrate multiple components in a smaller form factor.
Innovation Solution
The method involves forming integrated circuit packages using a process that simultaneously creates through encapsulant vias and redistribution lines, reducing the number of process steps and manufacturing costs, by depositing conductive material non-conformally in openings to ensure proper thickness and prevent crack formation, allowing for efficient integration of multiple dies in a stacked semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional packaging techniques are used for integrated circuits, then manufacturing reliability is maintained, but manufacturing cost increases and production time extends
Solution Approach 1:
The patent combines the formation of through-encapsulant vias and redistribution lines into a single simultaneous deposition process step. Multiple structures (via holes, via fills, redistribution line patterns) are formed in one process cycle rather than sequential steps, reducing manufacturing complexity and cost while maintaining structural integrity and electrical performance
Solution Approach 2:
The encapsulant material serves multiple functions: it provides mechanical protection for the die, acts as an insulating layer, forms the matrix for conductive via structures, and enables redistribution of electrical signals. This multi-functionality reduces the need for separate protective and interconnect structures, simplifying the overall packaging process
2Ease of manufacture
If the number of process steps is reduced to lower manufacturing cost, then manufacturing complexity decreases, but the risk of crack formation and manufacturing defects increases
Solution Approach 1:
The patent employs non-conformal deposition with controlled thickness parameters to ensure proper via fill while preventing crack formation. By carefully controlling deposition parameters (thickness, uniformity, material composition), the process achieves reliable via structures in a single step without the need for multiple sequential deposition cycles
Solution Approach 2:
The patent replaces traditional multi-step mechanical patterning and filling processes with a single conformal deposition process that simultaneously forms via structures and redistribution lines. This substitution reduces mechanical stress cycles that could cause crack formation while maintaining manufacturing precision
3Productivity
If conventional sequential processes are used for via and line formation, then manufacturing precision is maintained, but productivity decreases and production yield is reduced
Solution Approach 1:
The patent merges via formation and redistribution line formation into a single simultaneous deposition process. Patterned masks define both via openings and line patterns, and conductive material is deposited conformally across the entire surface in one step, forming both structures with consistent thickness and properties
Solution Approach 2:
The encapsulant is pre-formed with integrated via openings and line patterns defined by patterned masks before deposition. This preliminary patterning ensures precise alignment and dimensional control of both via and line structures, enabling simultaneous formation with controlled thickness and positioning
4Volume of moving object
If stacked semiconductor devices are used to reduce physical size, then integration density increases, but device complexity and packaging difficulty increase
Solution Approach 1:
The patent implements a nested structure where multiple dies are stacked vertically with each die packaged within an encapsulant that extends to accommodate upper dies. The encapsulant of lower dies serves as the substrate for mounting upper dies, creating a nested arrangement that maximizes space utilization and reduces overall device footprint
Solution Approach 2:
The encapsulant structure serves multiple functions across stacked dies: providing mechanical support for multiple dies, enabling electrical interconnection through through-encapsulant vias, facilitating heat dissipation pathways, and reducing overall device height. This multi-functionality simplifies the packaging process despite the increased complexity of stacked configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and increases production yield by minimizing process steps and crack formation, enabling the creation of smaller, more efficient integrated circuit packages with improved integration density and reduced latency.
Implementation Method 1
depositing conductive material non-conformally in openings to ensure proper thickness and prevent crack formation
Data Source
AI summary
An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.