Integrated Circuit Package Via Geometry for Delamination Resistance
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Solution Overview
Problem
The challenge in semiconductor packaging is the concentration of stress at the interfaces between through vias and encapsulants, leading to delamination and cracking, which reduces the reliability of the package.
Innovation Solution
Forming through vias with curved sidewalls, such as hourglass or bulged rectangle shapes, to distribute stress more evenly and reduce the risk of delamination and cracking at the via-encapsulant and via-under-bump metallurgy layer junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias with straight sidewalls are formed, then the manufacturing process is simple, but stress concentrates at the interfaces between through vias and encapsulants, leading to delamination and cracking
Solution Approach 1:
The patent applies curvature to the sidewalls of through vias, transitioning from straight sidewalls to curved sidewalls with specific radii of curvature. This curvature distributes stress more evenly at the interfaces between through vias and encapsulants, preventing stress concentration that leads to delamination and cracking. The curved geometry modifies the stress distribution pattern without fundamentally changing the via formation process.
2Reliability
If through vias with curved sidewalls are formed, then stress concentration is reduced and delamination is minimized, but the manufacturing process becomes more complex
Solution Approach 1:
The patent modifies the geometric parameters of through vias by introducing controlled curvature with specific radii of curvature. This parameter change transforms the sidewall geometry from straight to curved, achieving stress distribution optimization. The curvature radius is carefully selected to balance stress reduction benefits with manufacturing feasibility, ensuring the modified geometry can be achieved through standard fabrication processes.
Data Source
AI summary
In an embodiment, a device includes: an integrated circuit die including a die connector; a dielectric layer on the integrated circuit die; an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer to contact the die connector; a through via on the line portion of the under-bump metallurgy layer, the through via having a first curved sidewall proximate the die connector, the through via having a second curved sidewall distal the die connector, the first curved sidewall having a longer arc length than the second curved sidewall; and an encapsulant around the through via and the under-bump metallurgy layer.


