IC Package Thermal Dissipating Vias Power Plane Segmentation

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Solution Overview

Problem

Conventional IC packages primarily utilize the ground plane for heat dissipation, leaving the power plane without a direct pathway for heat dissipation, which limits the overall thermal performance of the package.

Innovation Solution

The IC package incorporates thermal dissipating vias connected to both non-power regions of the power plane and the ground plane, forming an internal heat spreader structure that enhances thermal performance by allowing heat generated by the semiconductor chip to be distributed throughout the package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If thermal dissipating vias are connected only to the ground plane, then the ground plane can dissipate heat, but the power plane cannot contribute to heat dissipation

Engineering Contradiction:
Improveheat dissipation capabilityVSAvoidutilization of power plane for heat dissipation
Core Design Contradiction:
TemperatureVSAdaptability or versatility

Solution Approach 1:

The power plane is segmented into power regions and non-power regions. The non-power regions are specifically designated for thermal dissipation functions, while power regions maintain electrical connectivity. This segmentation allows the power plane to serve dual purposes: electrical power distribution and heat dissipation, thereby resolving the contradiction between limited heat dissipation capability and underutilization of the power plane.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power plane is designed to perform multiple functions: it serves as both an electrical power distribution network and a thermal dissipation pathway. By incorporating non-power regions that are electrically isolated but thermally conductive, the power plane becomes a multi-functional structure that simultaneously handles power delivery and heat removal, addressing the contradiction between its traditional single function and potential versatility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If via clearance areas are created in the power plane and ground plane, then signal isolation is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvesignal isolationVSAvoidsubstrate fabrication complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The via clearance areas are pre-planned and integrated into the substrate design before manufacturing. By incorporating these clearance areas as part of the standard substrate fabrication process rather than as post-processing modifications, the patent minimizes additional manufacturing steps. The clearances are designed into the routing layer, allowing standard PCB manufacturing techniques to accommodate them without significant complexity increases, thus balancing signal isolation requirements with ease of manufacture.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively spreads heat generated by the semiconductor chip across the package, improving thermal performance by utilizing both the power and ground planes for heat dissipation, thereby enhancing the package's thermal management capabilities.

Implementation Method 1

thermal dissipating vias connected to both non-power regions of the power plane and the ground plane, forming an internal heat spreader structure that enhances thermal performance by allowing heat generated by the semiconductor chip to be distributed throughout the package

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS8031484B2IC packages with internal heat dissipation structures
Publication Date: 2011.10.04 HONG KONG APPLIED SCI & TECH RES INST
  • US8031484B2 patent drawing
  • US8031484B2 patent drawing
  • US8031484B2 patent drawing

AI summary

An IC package includes a substrate and a plurality of thermal dissipating vias perforating the substrate. The substrate includes a power plane, a ground plane, and a dielectric layer disposed between the power plane and the ground plane. The power plane includes a power region and a non-power region isolated from each other. The thermal dissipating vias are connected to the non-power regions of the power plane and to the ground plane.